LeCroy 4300B, Руководство оператора

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c. Enables the ADC pedestal injection circuit.
d. Applies a charge to the 16 ADCs that is proportional to the DC
voltage present on the front-panel TRV input.
e. At the end of the GATE starts conversation and switches the module
to the “busy” state.
The Test Reference Voltage (TRV) input is referenced to module ground.
The voltage applied on TRV may vary between 0 and +10.24 V which
corresponds to a charge of 0 to 512 pC per ADC. The test charge is not
affected by the common mode of the Common Virtual Ground with
respect to the module ground.
1.8 Pedestal Memory The Model 4300B contains an 8-bit, 16-word Pedestal where each word
corresponds to an ADC pedestal (or offset) value to be subtracted during
readout (maximum digital value 255). This memory may be loaded or
read via CAMAC in random access mode if the module is in the “ready”
state. The memory must be reloaded after a power-on, but is not affected
by clear functions.
Pedestal values are written in the memory with the CAMAC function
F(17), strobed by S1, and subaddresses from A(0) to A(15) correspond-
ing to channels 0 to 15. The 8 bits are written on lines W1 to W8. Read-
out of pedestal memory values is performed with F(1) and the same
subaddresses, A(0) to A(15). The 8 bits to be read out are sent on lines
R1 to R8. F(17) A(0) to A(15) and F(1) A(0) to A(15) are possible only
when the module is in the “ready” state; there is no Q response if they
cannot be accepted.
1.9 Status Register The Status Register is composed of two distinct sections. See Table
1.1.a. The low order 8-bit Virtual Station Number (VSN) determines the
address of the data source during readout, while the 8 other bits deter-
mine the readout modes.
The 15 bits of the Status Register are loaded by the CAMAC function
F(16) A(0) strobed by S1 with data written on lines W1 to W15. The value
of the Status Register may be read with the function F(0) A(0) on lines
R1 to R15. These two functions are possible only when the module is in
the “ready” state; there is no Q response if they cannot be accepted.
After a power-on, the state of the module is undetermined. The CAMAC
initialization function Z will enable the 7 command bits, but will not affect
the VSN register. The other clear functions have no effect on the Status
Register.
The functions of the 8 Status Register command bits are:
EPS: ECL port Pedestal Subtraction (W9,R9).
EPS = 1: subtracts, from each ADC channel, the value of
its pedestal (offset) contained within the Pedestal Memory
during the ECL port readout.
EPS = 0: no pedestal subtraction during ECL port readout.