31
2.1 GENERAL
The circuitry of the LeCroy Model 4300B FERA can be divided into the
following eleven basic parts:
a.
CLEAR and GATE functions
b.
Charge to time converters (16 channels)
c.
Test circuit
d.
Digital interpolators (16 channels)
e.
Real time counters (16 channels)
f.
Clock generator
g.
Pedestal memory
h.
Data compression and readout logic
i.
ECL port readout circuit
j.
CAMAC readout circuit
k.
CAMAC functions decoder
For a general overview, see the 4300B Block Diagram (Figure 2.1). This
block diagram gives only the principles of functioning - for further details,
consult the 4300B schematics located in the back pocket of this user’s
manual.
The Model 4300B adjustments which will be discussed in the following
paragraphs are located on the inner left-hand side of the module (cover
must be removed to access).
Warning:
Only the pedestal value adjustment (see Section 2.3) and the
ADC resolution adjustment (see Section 2.13) can be made without
modifying the modules performance. Other adjustments must not be
modified without adequate control.
2.2 CLEAR and
GATE Functions
The state of the BUSY flip-flop determines the two module states “ready”
and “busy”. It is cleared (“ready state) and remains at zero throughout
the duration of a CLEAR function. This CLEAR function is generated by
the front-panel CLEAR input or the CAMAC decoder (Z.S2, C.S2, F(9)
A(0).S2). This function also clears and maintains the CLEAR flip-flop of
the charge-to-time converters. In the “ready” state, the clock generator
and readout logic circuits are inhibited and the GATE input (or TEST) is
enabled. The GATE signal, generated by the front-panel GATE input or a
monostable triggered by the test function F(25) A(0).S2, initiates the
following command sequence:
a.
Sets the CLEAR flip-flop, suppressing clear of the charge-to-time
converters.
b.
Opens the charge-to-time converter gates.
c.
Enables the pedestal injection circuit.
d.
At the end of GATE, sets the BUSY flip-flop (“busy” state of module).
Setting the BUSY flip-flop results in the following functions:
a.
Inhibits the front-panel Gate input and on the CAMAC decoder;
inhibits all functions except data readout and clear.
b.
Triggers the two digitization control monostables.
OPERATING INSTRUCTIONS
Содержание 4300B
Страница 22: ...25 Figure 1 3 FERA SYSTEM CONNECTIONS ...
Страница 23: ...26 Figure 1 4 MODEL 4301 FERA DRIVER BLOCK DIAGRAM ...
Страница 24: ...27 Figure 1 5 LOCALIZATION OF REMOVABLE RESISTORS AND VGND GND JUMPER ...
Страница 34: ...38 Figure 2 1 MODEL 4300B BLOCK DIAGRAM ...
Страница 35: ...39 Figure 2 2 CHARGE TO TIME CONVERTER BLOCK DIAGRAM AND TIMING ...
Страница 36: ...40 Figure 2 3 TIME TO DIGITAL CONVERTER BLOCK DIAGRAM AND TIMING ...
Страница 37: ...41 APPENDIX 3 1 ECL DIFFERENTIAL I O LEVELS ...
Страница 38: ...42 APPENDIX 3 2 ECL SINGLE ENDED I O LEVELS ...
