LeCroy 4300B, Руководство оператора

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The Model 4300B will be in one of two states: “ready” or “busy”; depend-
ing on the GATE and CLEAR signals sent via either the front-panel or
CAMAC command. After a CLEAR, the module is in the “ready” state,
i.e., ready to receive a GATE (front-panel or test): the logic and the ADCs
are permanently cleared. It is only in the “ready” state that the Status
Register and the Pedestal Memory may be loaded or read via CAMAC.
After a GATE (front panel or test): the module changes to the “busy”
state and no other GATE signal will be accepted. The GATE disables the
reset, opens the ADCs and initiates the charge digitization logic. At the
end of the conversation time, data readout is enabled. At this time,
depending on the state of the Status Register and the ADC data values
to be read, one of four conditions may be present:
a. Data readout via ECL port and CAMAC. In this case, the ECL port
must be read first and only upon its completion can CAMAC readout
take place.
b. Data readout via ECL port only. In this case, only the ECL port is
enabled.
c. Data readout via CAMAC only. Here, the ECL port readout is not
enabled; CAMAC readout is enabled immediately at the end of
conversation.
d. No data to be read. In this case, no data readout is enabled.
To eliminate unwanted data or accept further GATE after data read out, a
CLEAR must be applied to the 4300B unit (see Figure 1.1).
1.3 Analog Inputs The 16 analog inputs are designed for negative signals with respect to a
floating common signal ground (Common Virtual Ground) which is
coupled to the module ground via capacitors. Input impedance is 50 or
100 ohm with respect to the Common Virtual Ground. All 16 inputs are
protected against positive signals by diodes connected to the module
ground, and against too high amplitude negative signals by diodes
connected to a -3 V potential. The Common Virtual Ground is also
protected against large swings of voltage by two diodes connected to the
module ground.
If the user wishes to connect the Common Virtual Ground to the module
ground, the 16 upper right hands pin (VGND, Common Virtual Ground)
may be connected to the lower 2 pins (GND, module ground), of the
input connector. Another option is to solder a jumper between the two
points designed for this function located on the printed circuit board (see
Figure 1.5).
1.4 Clear Function A clear is initiated by a front-panel CLEAR input and by CAMAC func-
tions Z, C or F(9) A(0) strobed by S2. Front-panel CLEAR and F(9) A(0)
have priority over the GATE signal and care must be taken not to gener-
ate any gate in coincidence with them. As a result, the GATE signal
duration would be modified.
These commands set a latch maintaining the clear level (“ready” state of
module) until the next GATE signal. The front ends of the ADCs require
at least 2
µ
s after a clear to guarantee a
±
1 count precision. They are