LeCroy 4300B, Руководство оператора

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Note: The valid channel address is also loaded in the Data Memory, but
these 4 bits are maintained at zero for ECL port and CAMAC readout
without compression or CAMAC random access. If the user wishes to
read the channel address in these readout modes, the clear may be
suppressed by disconnecting pin 13 of the integrated circuit located in
position 17 (74 ALS 874).
2.10 ECL Port
Readout Circuit
The command ER sets the REQ output, closes PASS output and if the
REN input is activated, opens the ECL port output gates and starts the
WST output, after a 40 nsec integrator delay. During the entire WAK
signal, this integrator is clamped and the WST output is reset. A protec-
tion loop prevents the WST length from being less than 40 nsec. The
trailing edge of the WST loads the next data in the Data Memory and
increments the Address Memory. After readout of the last data, detected
by the zero state of the Word Count Scaler, the command ER is released
and the CAMAC readout procedure is started.
2.11 CAMAC
Readout Circuit
The command CR sets the LAM flip-flop and enables the CAMAC
decoder for the function F(2). The function F(2) opens the output gates
on the R lines and enables the X and Q responses.
When the sequential readout is programmed (CSR = ON), the channel
addressing originates with the Address Scaler or the Address Memory
depending on the state of the command CCE. The trailing edge of the
function F(2).S2 loads the subsequent data into the Data Memory and
increments the Address Scaler and Word Count Scaler. After the readout
of the last data, detected by the zero state of the Word Counter Scaler,
the command CR is released and the LAM flip-flop is cleared.
When the random access readout is programmed (CSR = OFF), the
channel addressing is computed to the subaddress lines A1 through A4.
The function F(2) A(0 to 15) opens the addressed channel and starts the
RF oscillator. This oscillator provides the pulses necessary for the
loading of the data into the Data Memory. The Word Count Scaler is
inhibited to prevent the command CR from being released.
2.12 CAMAC
Functions Decoder
The decoding of CAMAC functions is done by two programmable logic
arrays (PAL) receiving CAMAC signals, the decoded subaddress A(0)
and the internal signals, BUSY, CR (CAMAC Readout enable) and LR
(LAM Request). Lines S1 and S2 are integrated to 50 nsec. These two
PALS generate all appropriate internal signals and the X and Q
responses.
The LAM is controlled by an RS flip-flop. This flip-flop is set by CR and
cleared by the CLEAR functions and F(10) A(0).S2. The LAM is inhibited
when the Status Register command CLE is OFF.
2.13 ADC Resolution
Adjustment
In order to modify the ADC resolution, the FS monostable must be
adjusted, by means of the FS potentiometer, and the jumpers must be
modified. Jumpers that are not utilized may be stored on the socket
provided for this purpose (i.e., under the P and O potentiometer).