LeCroy 4300B, Руководство оператора

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1.1 General The LeCroy Model 4300B FERA contains 16 independent charge-to-
digital converters with common GATE and common CLEAR.
Four basic factory options are available:
a. 8 or 9 bits with 100 ohm impedance
b. 8 or 9 bits with 50 ohm input impedance
c. 10 or 11 bits with 100 ohm input impedance
d. 10 or 11 bits with 50 ohm input impedance.
The options a, b and c are only produced for large quantities. The
resolution on each of the above versions may be adjusted via jumpers
and an internal potentiometer (see Section 2.13 for details).
1.2 Specifications
PRODUCT DESCRIPTION
LeCroy Input Resolution Conversion Range Sensitivity Digital Values
4300B Impedance Time Typical Typical Full Over
MOD Scale Flow
ohms bits
µ
sec pC pC/count counts counts
100 100 8 1.8 128 0.5 255 2047
500 50
110 100 9 2.8 256 0.5 511 2047
510 50
200 100 10 4.8 256 0.25 1023 2047
600 50
210 100 11 8.5 480 0.25 1919 2047
610 50
An 8-bit register (Status Register) and a memory (Pedestal Memory),
containing the individual pedestal (or offset) values to be subtracted from
each ADC, allow different readout modes of the 16 digitized ADC values.
Both the Status Register and Pedestal Memory must be previously
loaded via CAMAC. Data may be read out either via the CAMAC
dataway or the ECL port. The state of the Status Register determines the
readout modes. The ECL port output, located on the front-panel, is first
activated and delivers ADC data sequentially in words of 16 bits (8 to 11
bits of data plus 4 subaddress) at differential ECL levels. When data are
ready to be read at the ECL port, the REQ output is activated.
In CAMAC mode, data are also read out in 16-bit words in either random
access or sequential CAMAC readout (Q stop mode). The CAMAC
readout can only be carried out after completion of ECL port readout.
When data are ready for readout via CAMAC dataway, a LAM may be
generated and there is a Q response to the readout function F(2). The
data read out mode via these two ports may be independently selected
and programmed to be in one of three states: 1) raw; 2) with the pedes-
tal subtracted; or 3) compacted, i.e., all data < 1 are eliminated (Zero
suppression).
A system for testing the 16 ADCs is incorporated in the Model 4300B.
The test is initiated by the CAMAC command F(25) A(0). This command
opens the ADC GATEs and applies, at the input of each one, a charge
proportional to the continuous voltage that must be given on the front
panel TRV input.