LeCroy 4300B, Руководство оператора

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automatically cleared at the end of conversation after digitized charges
have been memorized. Thus, a 2
µ
s delay before a new GATE is only
necessary when the CLEAR command is used during conversation. After
power-on, a clear function must be applied for the module to be in the
“ready” state.
1.5 External Gate
Input (GATE)
A GATE command is effective only if the module is in the “ready” state
and if the CLEAR command is released. The GATE input is inhibited
when the I (CAMAC Inhibit) line is ON. A 100 ns integrator is placed on
the I line.
A valid GATE signal commands the following functions:
a. Releases the clear on the ADC front ends.
b. Opens ADC gate for its entire duration.
c. Enables ADC pedestal injection circuit.
d. The end of the GATE starts conversation, switches the module to the
“busy” state and inhibits the GATE input.
The GATE signal must precede analog input signals by a minimum of
20 ns and its length may vary from 50 ns to 500 ns. Use of a GATE
longer than 500 ns is possible, but it may require adjustment of ADC
pedestals (see Sections 1.6 and 2.3).
1.6 ADC Pedestals The 16 ADC pedestals are generated by the injection of a small charge
at the leading edge of the GATE. The pedestal value may be adjusted via
an internal potentiometer, 0 adjustment. A common circuit compensates,
to a large degree, the variations of the pedestals with respect to GATE
width.
The Model 4300B is adjusted so that the pedestals remain between 1
and 13 pC for GATE durations of 50 ns to 500 ns. For a GATE larger
than 500 ns, some ADCs channels may have pedestals below 0 pC. The
charge injected by the O adjustment potentiometer must be increased to
obtain at least 1 pC.
The pedestals may be subtracted from the ADC value during ECL port or
CAMAC readout, independently.
1.7 Test Function The test function is initiated by the CAMAC command F(25) A(0) strobed
by S2, when accepted, Q response is given. This function is accepted
only when the module is in the “ready” state; no Q response will be given
if the command is not accepted.
The test function controls the following operations:
a. Releases the clear on the front end of the ADCs.
b. Opens the GATE for a duration of 550 ns, during which time no
signal is allowed on any of the analog inputs, although the cable may
remain connected. The gate input may, but need not, be blocked by
the CAMAC command I.