LAPIS Semiconductor ML610472, Руководство пользователя

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 7 Time Base Counter
7-5
7.2.3 High-Speed Time Base Counter Divide Register (HTBDR)
Address: 0F00BH
Access: R/W
Access size: 8-bit
Initial value: 00H
7 6 5 4 3 2 1 0
HTBDR ― ― ― ― HTD3 HTD2 HTD1 HTD0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
HTBDR is a special function register (SFR) to set the dividing ratio of the 4-bit, 1/n counter.
[Description of Bits]
•
HTD3-HTD0 (bits 3-0)
The HTD3-HTD0 bits are used to set the dividing ratio of the 4-bit, 1/n counter. The frequency divide ratios
selectable include 1/1 to 1/16.
Description
HTD3 HTD2 HTD1 HTD0
Dividing ratio
Frequency of
HTBCLK (*1)
0 0 0 0 1/16 (initial value) 31kHz
0 0 0 1 1/15 33kHz
0 0 1 0 1/14 36kHz
0 0 1 1 1/13 38kHz
0 1 0 0 1/12 42kHz
0 1 0 1 1/11 45kHz
0 1 1 0 1/10 50kHz
0 1 1 1 1/9 56kHz
1 0 0 0 1/8 63kHz
1 0 0 1 1/7 71kHz
1 0 1 0 1/6 83kHz
1 0 1 1 1/5 100kHz
1 1 0 0 1/4 125kHz
1 1 0 1 1/3 167kHz
1 1 1 0 1/2 250kHz
1 1 1 1 1/1 500kHz
*1: Indicates the frequency when the high-speed oscillation clock, HSCLK, is 500 kHz.