LAPIS Semiconductor ML610472, Руководство пользователя

Страница: 126 / 281

ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 9 Timer
9-12
9.3 Description of Operation
9.3.1 Timer mode operation
The timer counters (TMnC) are set to an operating state (TnSTAT are set to “1”) on the first falling edge of the timer
clocks (TnCK) that are selected by the Timer 2, Timer 3 control register 0 (TMnCON0) when the TnRUN bits of Timer
2, Timer 3 control register 1 (TMnCON1) are set to “1” and increment the count value on the 2nd falling.
When the count value of TM2C, TM3C and the Timer 2, Timer 3 data register (TMnD) coincide, Timer 2, Timer 3
interrupt (TMnINT) occurs on the next timer clock falling edge, TMnC are reset to “00H” and incremental counting
continues.
When the TnRUN bits are set to “0”, TMnC stop counting after counting once the falling of the timer clock (TnCK).
Confirm that TMnC has been stopped by checking that the TnSTAT bit of the Timer 2, Timer 3 control register 1
(TMnCON1) is “0”.
When the TnRUN bits are set to “1” again, TMn restart incremental counting from the previous values.
To initialize TMnC to “00H”, perform write operation in TMnC.
The timer interrupt period (T
TMI
) is expressed by the following equation.
TMnD + 1
T
TMI
=
TnCK (Hz)
(n=2, 3)
TMnD: Timer 2, Timer 3 data register (TMnD) setting value (01H to 0FFH)
TnCK: Clock frequency selected by the Timer 2, Timer 3 control register 0 (TMnCON0)
After the TnRUN bits are set to “1”, timers are synchronized by the timer clock and counting starts so that an error of a
maximum of 1 clock period occurs until the first timer interrupt. The timer interrupt periods from the second time are
constant.
Figure 9-2 shows the operation timing diagram of Timer 2, Timer 3.
Figure 9-2 Operation Timing Diagram of Timer 2, Timer 3
Note:
Even if “0” is written to the TnRUN bits, counting operation continues up to the falling edge (the timer 0 to 3 status
flag (TnSTA) is in a “1” state) of the next timer clock pulse. Therefore, the Timer 2, Timer 3 interrupt (TMnINT)
may occur.
TMnC
XX
00
88
TMnD
TMnINT
TnSTAT
Write TMnC
TnCK
TnRUN
01
02
87
88 00
62 5F 60
61
01
88 88
(n=
2,
3)
T
TMI