LAPIS Semiconductor ML610472, Руководство пользователя

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 5 Interrupt
5-17
A-2: When a subroutine is called by the program in executing an interrupt routine
A-2-1: When multiple interrupts are disabled
•Processing immediately after the start of interrupt routine execution
Specify the “PUSH LR” instruction to save the subroutine return address in the stack.
•Processing at the end of interrupt routine execution
Specify “POP LR” immediately before the RTI instruction to return from the interrupt processing after
returning the subroutine return address to LR.
A-2-2: When multiple interrupts are enabled
•Processing immediately after the start of interrupt routine execution
Specify "PUSH LR, ELR, EPSW" to save the interrupt return address, the subroutine return address, and
the EPSW status in the stack.
•Processing before the master interrupt enable(MIE) bit is set
Specify “RB Exx” to invalidate the accepted interrupt. (Exx: the accepted interrupt enable flag)
•Processing at the end of interrupt routine execution
Specify “DI” not to execute the same interrupt routine.
Specify “SB Exx” to validate the accepted interrupt. (Exx: the accepted interrupt enable flag)
Specify “POP PC, PSW, LR” instead of the RTI instruction to return the saved data of the interrupt return
address to PC, the saved data of EPSW to PSW, and the saved data of LR to LR.
Example of description: Status A-2-2
Intrpt_A-2-2; ; Start
PUSH
ELR,EPSW,LR ; Save ELR, EPSW, and LR at
the beginning
:
RB Exx
; Invalidate the accepted
interrupt (*1)
EI ; Enable interrupt (*2) Sub_1; ;
: DI ; Disable interrupt
: :
: :
BL Sub_1 ; Call subroutine Sub_1 EI ; Enable interrupt
: RT ; Return PC from LR
: ; End of subroutine
:
DI ; Disable interrupt
SB Exx
; Validate the accepted
interrupt
POP PC,PSW,LR ; Return PC from the stack
; Return PSW from the stack
; Return LR from the stack
; End
(*1) When multiple interrupts are enabled, please set the accepted interrupt enable flag to “0” to prevent
the occurrence of the accepted interrupt.
(*2) After enabling interrupt, not only a higher-priority interrupt than the accepted interrupt but also a
lower-priority interrupt than that occurs.