LAPIS Semiconductor ML610472, Руководство пользователя

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 5 Interrupt
5-10
5.2.9 Interrupt Request Register 4 (IRQ4)
Address: 0F01CH
Access: R/W
Access size: 8-bit
Initial value: 00H
7 6 5 4 3 2 1 0
IRQ4 — — QRAD — — — — QUA0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
IRQ4 is a special function register (SFR) to request an interrupt for each interrupt source.
Each IRQ4 request flag is set to “1” regardless of the IE4 and MIE values when an interrupt is generated. In this case, an
interrupt is requested to the CPU when the related flag of the interrupt enable register (IE4) is set to “1” and the master
interrupt enable flag (MIE) is set to “1”.
By setting the IRQ4 request flag to “1” by software, an interrupt can be generated.
The corresponding flag of IRQ4 is set to “0” by hardware when the interrupt request is accepted by the CPU.
[Description of Bits]
•
QUA0 (bit 0)
QUA0 is the request flag for the UART0 interrupt (UA0INT).
QUA0 Description
0 No request (initial value)
1 Request
•
QRA0 (bit 5)
QMD0 is the request flag for the RC oscillation type A/D converter interrupt (RADINT).
QRA0 Description
0 No request (initial value)
1 Request
Note:
When an interrupt is generated by the write instruction to the interrupt request register (IRQ4) or to the interrupt
enable register (IE4), the interrupt shift cycle starts after the next 1 instruction is executed.