LAPIS Semiconductor ML610472, Руководство пользователя

Страница: 174 / 281

ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 13 Port 2
13-1
13. Port 2
13.1 Overview
This LSI includes 1-bit Port 2 (P20, P21) dedicated to output.
Port 2 can output low-speed clock (LSCLK), high-speed clock (OUTCLK) as a secondary function. For the clock output,
see Chapter 6, "Clock Generation Circuit."
13.1.1 Features
•
Allows direct LED drive.
•
Allows selection of high-impedance output mode, P-channel open drain output mode, N-channel open drain output
mode, or CMOS output mode for each bit.
•
Allows output of low-speed clock (LSCLK)., high-speed clock (OUTCLK) as a secondary function.
13.1.2 Configuration
Figure 13-1 shows the configuration of Port 2.
P2D : Port 2 data register
P2CON0 : Port 2 control register 0
P2CON1 : Port 2 control register 1
P2MOD
: Port 2 mode register
Figure 13-1 Configuration of Port 2
13.1.3 List of Pins
Pin name I/O Primary function Secondary function
P20/LED0/LSCLK O Output port Low-speed clock output (LSCLK)
P21/LED1/OUTCLK*
1
O Output port High-speed clock output (OUTCLK)
*1:
In 48-pin plastic TQFP, P21 pin is not available.
Data bus
LSCLK
OUTCLK
P20,P21
P2MOD
P2CON0
P2CON1
V
DD
V
DD
V
SS
V
SS
2
2
Port2
Output
Controller
P2D