LAPIS Semiconductor ML610472, Руководство пользователя

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 17 RC Oscillation Type A/D Converter
17-11
(10000H – nA0)
(+1) (+2) (+3)
0FFFCH 0000H
t
BSCLK
h
Overflow
Gate time
nA0·t
BSCLK
c
0000H 0001H 0002H nB0 – 2 nB0 – 1
nB0
d
nB0·t
RCCLK
i
(Interrupt request)
t
RCCLK
RARUN
BSCLK
RCON
Counter A
CR oscillator circuit
Input waveform
IN0/IN1
RCCLK
Counter B
RADINT
nA0: Reference count value
nB0: Measurement count value
g
0FFFDH
0FFFEH 0FFFFH
Figure 17-3 Operation Timing in Counter A Reference Mode
(2) Operation in Counter B reference mode
Figure 17-4 shows the operation timing in Counter B reference mode.
Following is an example of operation procedure in Counter B reference mode:
c
Preset to Counter B (RADCB1 and RADCB0) the value obtained by subtracting the count value “nB1” from the
maximum value + 1 (10000H). The product of the count value “nB1” and the RCCLK clock cycle indicates the gate
time.
d
Preset “0000H” to Counter A (RADCA1 and RADCA0).
e
Set the OM3–OM0 bits of RADMOD to desired oscillation mode. (See Table 17-1.)
f
Set the RADI bit of RADMOD to “1” to specify generating of an interrupt request signal by Counter B overflow.
g
Set the RARUN bit of RADCON to “1” to start A/D conversion.
When the RARUN bit is set to “1” and the RCON signal (signal synchronized with the fall of the base clock) is set to”1”,
the RC oscillator circuit starts operation and Counter B starts counting of the RC oscillator clock (RCCLK). When
Counter B overflows, the RARUN bit is automatically reset (
h
) and conversion operation terminates. At the same time,
an RC-ADC interrupt request (RADINT) occurs. (
i
)
When the RCON signal is set to “1”, Counter A starts counting of the base clock (BSCLK). When the RARUN bit is
reset due to overflow of Counter B, Counter A stops counting.
The final count “nA1” of Counter A is the CLK count value during the gate time “nB1 x t
RCCLK
” and is expressed by the
following expression:
t
RCCLK
1
nA1
≅
nB1
•
t
BSCLK
∝
f
RCCLK