LAPIS Semiconductor ML610472, Руководство пользователя

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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 10 Watchdog Timer
10-1
10. Watchdog Timer
10.1 Overview
This LSI incorporates a watchdog timer (WDT) that operates at a system reset unconditionally (free-run operation) in
order to detect an undefined state of the MCU and return from that state.
If the WDT counter overflows due to the failure of clearing of the WDT counter within the WDT overflow period, the
watchdog timer requests a WDT interrupt (non-maskable interrupt). When the second overflow occurs, the watchdog
timer generates a WDT reset signal and shifts the mode to a system reset mode.
For interrupts see Chapter 5, “Interrupt,” and for WDT interrupt see Chapter 3, “Reset Function”.
10.1.1 Features
•
Non-maskable interrupt
•
Free running (cannot be stopped)
•
One of four types of overflow periods (125ms, 500ms, 2s, and 8s) selectable by software
•
Reset generated by the second overflow
10.1.2 Configuration
Figure 10-1 shows the configuration of the watchdog timer.
WDTCON : Watchdog timer control register
WDTMOD : Watchdog timer mode register
Figure 10-1 Configuration of Watchdog Timer
Data bus
WDP
D Q
R
QN
“5AH”
Perform
detection
“0A5H”
Perform
detection
WDT counter
R
Reset
interrupt
control
WDT reset
WDTINT
Non-maskable interrupt
RESET_S
System reset
T256HZ
WDTCON Write
WDT overflow
WDTMOD
WDTCON