LAPIS Semiconductor ML610472, Руководство пользователя

Страница: 120 / 281

ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 9 Timer
9-6
9.2.4 Timer 2 Counter Register (TM2C)
Address: 0F039H
Access: R/W
Access size: 8-bit
Initial value: 00H
7 6 5 4 3 2 1 0
TM2C T2C7 T2C6 T2C5 T2C4 T2C3 T2C2 T2C1 T2C0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
TM2C is a special function register (SFR) that functions as an 8-bit binary counter.
When write operation to TM2C is performed, TM2C is set to “00H”. The data that is written is meaningless.
In 16-bit timer mode and 16-bit timer frequency measurement mode, if write operation is performed to either the
low-order TM2C or high-order TM3C, both the low order and the high order are set to “0000H”.
During timer operation, the TM2C content may not be read depending on the conditions of the timer clock and the
system clock.
Table 9-1 shows whether a TM2C read is enabled or disabled during timer operation for each condition of the timer
clock and system clock.
Table 9-1 TM2C Read Enable/Disable during Timer Operation
Timer clock
T2CK
System clock
SYSCLK
TM2C read enable/disable
LSCLK LSCLK Read enabled.
LSCLK HSCLK
Read enabled. However, to prevent the reading of undefined data
during incremental counting, read TM2C twice and check that the
results match.
HTBCLK LSCLK Read disabled.
HTBCLK HSCLK Read enabled.
LSCLK
External clock
HSCLK
Read disabled.