Keysight 34401A, Руководство по обслуживанию

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The counter register is used to capture either
ADC
slope count at the
COMP
input or frequency count at the
FREQIN
input. The
COMP
input
functions as both a clocked comparator and the slope counter input for
the
ADC
. In both cases the counter register captures the lower 8 bits of a
24-bit counter. The upper 16 bits of the count are captured by the
SYNC
input to
U500
. The serial register is used to send and receive serial data
bytes from the main
CPU
to the 40 bit (5 x 8 bits) measurement
configuration register comprised of
U309
,
U311
,
U150
, and
U101
or to
communicate with the front panel processor. The serial register is
multiplexed to these two circuits. The transmission rate is selected to
1.5 M bits/second for the measurement configuration registers and to
93.75 k bits/second for communication with the front panel processor.
The general serial interface is a 3-bit interface as shown below.
Serial data is received simultaneously as serial data is clocked out.
The measurement configuration readback data (
SERRBK
) is only
checked during self-test operation. Front panel data is exchanged in
both directions whenever a byte is sent from
U501
. The measurement
configuration register data is strobed to outputs by
U500
signal
SERSTB
.
Interrupts from the front panel are detected by
U501
and signaled to the
processor by
CHINT
. The processor line
FPINT
signals the front panel
processor that
U501
has data to send.
The gate array (
U501
) internal status register reports a serial port busy
bit and 4 bits of time interpolation data. The time interpolation data is
used to extend the time counting resolution of processor
U500
during
ADC
conversions and frequency measurements.
The multimeter’s calibration correction data are stored in a 128 x 16 bit
non-volatile electrically erasable
RAM
,
EERAM U505
. The
EERAM
read/write data is accessed by a 4-bit serial protocol controlled by
U500
.
U501 Internal Signal Measurement Configuration Signals Front Panel Signals
Serial Clock
Data OUT (send)
Data IN (receive) SERCK
SERDAT0
SERRBK XFPSK
FPDI
FPDO
Chapter 5 Theory of Operation
Floating Logic
104