JAI AD-131GE, Руководство пользователя

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AD-131GE
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coincident with each other. The ― Sequence Table Reset 0 ‖ and ― Sequence Table Reset 1 ‖ reset
the sequential settings at the rising edge of FVAL.
7.1.2 12-bit Counter
A camera pixel clock can be used as a source. The counter has a ―Divide by N‖, where N has the
range 1 through 4096, allowing a wide range of clock frequencies to be programmed. Setting
value 0 is bypass, setting value 1 is 1/2 dividing, and setting value 4095 is 1/4096 dividing. As
the pixel clocks for the AD-131GE are 51.324 MHz, the output frequency is varied from 51.324
MHz to 12.53 KHz.
7.1.3 Pulse Generators (0 to 3)
Each pulse generator consists of a 20-bit counter. The behavior of these signals is defined by
their pulse width, start point and end point.
The pulse generator signals can be set in either triggered or periodic mode (Free Run).
In triggered mode, the pulse is triggered by the rising edge, falling edge, high level or low level
of the input signal. In periodic mode, the trigger continuously generates a signal that is based
on the configured pulse width, starting point and end point.
7.2. Opto-isolated Inputs/Outputs
The control interface of the C3 GigE Vision camera series has opto-isolated inputs and outputs,
providing galvanic separation between the camera
’ s inputs/outputs and peripheral equipment.
In addition to galvanic separation, the opto-isolated inputs and outputs can cope with a wide
range of voltages; the voltage range for inputs is +3.3V to +24V DC whereas outputs will handle
+5V to +24V DC.
Fig.10 Photo coupler
7.2.1 Recommended External Input circuit diagram for customer
Fig.11 External Input Circuit
、
OPT IN 1 and 2