REL0.2
Page 21 of 110
iWave Systems Technologies Pvt. Ltd.
Zynq Ult MPSoC (ZU11/17/19EG) SOM DevKit Hardware User Guide
Table 4: PCIe x4 Connector Pin Assignment
Pin No
Pin Name
Signal Name
Signal Type/
Termination
Description
A1
PRSNT1#
PRSNT1#
O, 3.3V CMOS
Default Grounded.
A2
+12V
VCC_12V
O, 12V Power
12V Supply Voltage.
A3
+12V
VCC_12V
O, 12V Power
12V Supply Voltage.
A4
GND
GND
Power
Ground.
A5
TCK
NA
NA
NC.
A6
TDI
NA
NA
NC.
A7
TDO
NA
NA
NC.
A8
TMS
NA
NA
NC.
A9
+3V3
VCC_3V3
O, 3.3V Power
3.3V Supply Voltage.
A10
+3V3
VCC_3V3
O, 3.3V Power
3.3V Supply Voltage.
A11
PERST#
PL_E3_LVDS94_L3P
O, 3.3V CMOS
PCIe Reset through PL Bank IO.
A12
GND
GND
Power
Ground.
A13
PCIe_REFCLKP
O, DIFF
100MHz PCIe Reference Clock positive.
A14
REFCLK-
PCIe_REFCLKn
O, DIFF
100MHz PCIe Reference Clock negative.
A15
GND
GND
Power
Ground.
A16
PERp0
PS_MGTRRXP0_505
I, DIFF
PCIe Lane0 Receive pair positive.
A17
PERn0
PS_MGTRRXN0_505
I, DIFF
PCIe Lane0 Receive pair negative.
A18
GND
GND
Power
Ground.
A19
RSVD
NA
NA
NC.
A20
GND
GND
Power
Ground.
A21
PERp1
PS_MGTRRXP1_505
NA
PCIe Lane1 Receive pair positive.
A22
PERn1
PS_MGTRRXN1_505
NA
PCIe Lane1 Receive pair negative
A23
GND
GND
Power
Ground.
A24
GND
GND
Power
Ground.
A25
PERp2
PS_MGTRRXP2_505
NA
PCIe Lane2 Receive pair positive.
A26
PERn2
PS_MGTRTXN2_505
NA
PCIe Lane2 Receive pair negative.
A27
GND
GND
Power
Ground.
A28
GND
GND
Power
Ground.
A29
PERp3
PS_MGTRRXP3_505
NA
PCIe Lane3 Receive pair positive.
A30
PERn3
PS_MGTRRXN3_505
NA
PCIe Lane3 Receive pair negative.
A31
GND
GND
Power
Ground.
A32
RSVD
NA
NA
NC.
B1
+12V
VCC_12V
O, 12V Power
12V Supply Voltage.
B2
+12V
VCC_12V
O, 12V Power
12V Supply Voltage.
B3
RSVD
NA
NA
NC.
B4
GND
GND
Power
Ground.
B5
SMCLK
I2C0_SCL(PS_MIO10_500)
O, 3.3V CMOS
SMB Clock.
B6
SMDAT
I2C0_SDA(PS_MIO11_500)
IO, 3.3V CMOS
SMB DATA.
B7
GND
GND
Power
Ground.
B8
+3V3
VCC_3V3
O, 3.3V Power
3.3V Supply Voltage.
B9
TRST#
NA
NA
NC.