REL0.2
Page 22 of 110
iWave Systems Technologies Pvt. Ltd.
Zynq Ult MPSoC (ZU11/17/19EG) SOM DevKit Hardware User Guide
Pin No
Pin Name
Signal Name
Signal Type/
Termination
Description
B10
3V3AUX
VCC_3V3_AUX
O, 3.3V Power
3.3V Supply Voltage
B11
WAKE#
PL_E2_LVDS94_L3N
O, 3.3V CMOS
PCIe Wake through PL Bank IO.
B12
RSVD
NA
NA
NC.
B13
GND
GND
Power
Ground.
B14
PETp0
PS_MGTRTXP0_505
O, DIFF
PCIe Lane0 Transmit pair positive.
B15
PETn0
PS_MGTRTXN0_505
O, DIFF
PCIe Lane0 Transmit pair negative.
B16
GND
GND
Power
Ground.
B17
PRSNT2
NA
NA
NC.
B18
GND
GND
Power
Ground.
B19
PETp1
PS_MGTRTXP1_505
NA
PCIe Lane1 Transmit pair positive.
B20
PETn1
PS_MGTRTXN1_505
NA
PCIe Lane1 Transmit pair negative
B21
GND
GND
Power
Ground.
B22
GND
GND
Power
Ground.
B23
PETp2
PS_MGTRTXP2_505
NA
PCIe Lane2 Transmit pair positive.
B24
PETn2
PS_MGTRTXN2_505
NA
PCIe Lane2 Transmit pair negative
B25
GND
GND
Power
Ground.
B26
GND
GND
Power
Ground.
B27
PETp3
PS_MGTRTXP3_505
NA
PCIe Lane3 Transmit pair positive.
B28
PETn3
PS_MGTRTXN3_505
NA
PCIe Lane3 Transmit pair negative
B29
GND
GND
Power
Ground.
B30
RSVD
NA
NA
NC.
B31
PRSNT#2
NA
NA
NC.
B32
GND
GND
Power
Ground.