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iWave Systems Technologies Pvt. Ltd.
Zynq Ult MPSoC (ZU11/17/19EG) SOM DevKit Hardware User Guide
The PS-GTR Lane selection switch (SW6) setting and corresponding interface selection option is explained below.
Table 3: PS-GTR Lane Selection Switch Setting
PS-GTR Lanes
PS-GTR Lane Selection Switch (SW6)
Switch Bit
Number
Switch Bit Position
OFF
ON
Lane0
Bit1
PS-GTR Lane0 is connected to Lane0
of PCIe x4 connector (default)
PS-GTR Lane0 is connected to Lane1
of DP connector
Lane1
Bit2
PS-GTR Lane1 is connected to Lane1
of PCIe x4 connector
PS-GTR Lane1 is connected to Lane0
of DP connector (default)
Lane2
Bit3
PS-GTR Lane2 is connected to Lane2
of PCIe x4 connector
PS-GTR Lane2 is connected to Lane1
of USB3.0 Type-C connector (default)
Lane3
Bit4
PS-GTR Lane3 is connected to Lane3
of PCIe x4 connector
PS-GTR Lane3 is connected to M.2
SATA connector (default)
Figure 7: PS-GTR Lane Selection Switch