Error Messages and Beep Codes
77
Table 47. Port 80h POST Codes
(continued)
Port 80 Code
Progress Code Enumeration
PEI after MRC
0x2A
Start to Program MTRR Settings
0x2B
Done Programming MTRR Settings
PEIMs/Recovery
0x31
Crisis Recovery has initiated
0x33
Loading recovery capsule
0x34
Start recovery capsule/ valid capsule is found
CPU Initialization
CPU PEI Phase
0x41
Begin CPU PEI Init
0x42
XMM instruction enabling
0x43
End CPU PEI Init
CPU PEI SMM Phase
0x44
Begin CPU SMM Init smm relocate bases
0x45
Smm relocate bases for APs
0x46
End CPU SMM Init
CPU DXE Phase
0x47
CPU DXE Phase begin
0x48
Refresh memory space attributes according to MTRRs
0x49
Load the microcode if needed
0x4A
Initialize strings to HII database
0x4B
Initialize MP Support
0x4C
CPU DXE Phase End
CPU DXE SMM Phase
0x4D
CPU DXE SMM Phase begin
0x4E
Relocate SM bases for all APs
0x4F
CPU DXE SMM Phase end
IO BUSES
0x50
Enumerating PCI buses
0x51
Allocating resources to PCI bus
0x52
Hot Plug PCI controller initialization
USB
0x58
Resetting USB bus
0x59
Reserved for USB
ATA/ATAPI/SATA
0x5A
Resetting PATA/SATA bus and all devices
0x5B
Reserved for ATA
continued
Содержание DB75EN
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