Intel Celeron Series, Спецификация

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Errata
R
40 Intel
®
Celeron
®
Processor in the 478-Pin Package Specification Update
AC56. A Timing Marginality in the Instruction Decoder Unit May Cause an
Unpredictable Application Behavior and/or System Hang
Problem:
A timing marginality may exist in the clocking of the instruction decoder unit which leads to a
circuit slowdown in the read path from the Instruction Decode PLA circuit. This timing
marginality may not be visible for some period of time.
Implication:
When this erratum occurs, an incorrect instruction stream may be executed resulting in an
unpredictable application behavior and/or system hang.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum. BIOS must load the
microcode update during the BIOS POST time prior to memory initialization.
Status:
For the steppings affected, see the Summary
Tables of Changes.
AC57. Memory Aliasing of Pages as Uncacheable Memory Type and Write Back
(WB) May Hang the System
Problem:
When a page is being accessed as either Uncacheable (UC) or Write Combining (WC) and WB,
under certain bus and memory timing conditions, the system may loop in a continual sequence of
UC fetch, implicit writeback, and Request For Ownership (RFO) retries.
Implication:
This erratum has not been observed in any commercially available operating system or
application. The aliasing of memory regions, a condition necessary for this erratum to occur, is
documented as being unsupported in the
IA-32 Intel
®
Architecture Software Developer's Manual
,
Volume 3
,
section 10.12.4, Programming the PAT. However, if this erratum occurs the system
may hang.
Workaround:
The pages should not be mapped as either UC or WC and WB at the same time.
Status:
For the stepping affected, see the
Summary Table of Changes.
AC58. Using STPCLK and Executing Code from Very Slow Memory Could Lead to
a System Hang
Problem:
The system may hang when the following conditions are met:
1.
Periodic STPCLK mechanism is enabled via the chipset
2.
Hyper-Threading Technology is enabled
3. One logical processor is waiting for an event (i.e. hardware interrupt)
4. The other logical processor executes code from very slow memory such that every code fetch
is deferred long enough for the STPCLK to be re-asserted.
Implication:
If this erratum occurs, the processor will go into and out of the sleep state without making
forward progress, since the logical processor will not be able to service any pending event. This
erratum has not been observed in any commercial platform running commercial software
.
Workaround:
None
Status:
For the steppings affected, see the
Summary Tables of Changes.