Errata
R
Intel
®
Celeron
®
Processor in the 478-Pin Package Specification Update
37
AC47.
Changes to CR3 Register Do Not Fence Pending Instruction Page Walks
Problem:
When software writes to the CR3 register, it is expected that all previous/outstanding code, data
accesses and page walks are completed using the previous value in CR3 register. Due to this
erratum, it is possible that a pending instruction page walk is still in progress, resulting in an
access (to the PDE portion of the page table) that may be directed to an incorrect memory address.
Implication:
The results of the access to the PDE will not be consumed by the processor so the return of
incorrect data is benign. However, the system may hang if the access to the PDE does not
complete with data (e.g. infinite number of retries).
Workaround:
It is possible for the BIOS to have a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
AC48.
Processor Provides a 4-Byte Store Unlock after an 8-Byte Load Lock
Problem:
When the processor is in the Page Address Extension (PAE) mode and detects the need to set the
Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte
load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte
store unlock occurs. Correct data is provided since only the lower bytes change, however
external logic monitoring the data transfer may be expecting an 8 byte load lock.
Implication:
No known commercially available chipsets are affected by this erratum.
Workaround:
None identified at this time
Status:
For the steppings affected, see the
Summary Tables of Changes
AC49.
System Bus Interrupt Messages without Data Which Receive a HardFailure
Response May Hang the Processor
Problem:
When a system bus agent (processor or chipset) issues an interrupt transaction without data onto
the system bus and the transaction receives a HardFailure response, a potential processor hang can
occur. The processor, which generates an inter-processor interrupt (IPI) that receives the
HardFailure response, will still log the MCA error event cause as HardFailure, even if the APIC
causes a hang. Other processors, which are true targets of the IPI, will also hang on hardfail-
without-data, but will not record an MCA HardFailure event as the cause. If a HardFailure
response occurs on a system bus interrupt message with data, the APIC will complete the
operation so as not to hang the processor.
Implication:
The processor may hang.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
