Intel Celeron Series, Спецификация

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Errata
R
28 Intel
®
Celeron
®
Processor in the 478-Pin Package Specification Update
AC22. SQRTPD and SQRTSD May Return QNaN Indefinite Instead of Negative
Zero
Problem:
When DAZ mode is enabled, and a SQRTPD or SQRTSD instruction has a negative denormal
operand, the instruction will return a QNaN indefinite when the specified response should be a
negative zero.
Implication:
When this erratum occurs, the instruction will return a QNaN indefinite when a negative zero is
expected.
Workaround:
Ensure that negative denormals are not used as operands to the SQRTPD or SQRTSD instructions
when DAZ mode is enabled. Software could enable FTZ mode to ensure that negative denormals
are not generated by computation prior to execution of a SQRTPD or SQRTSD instruction.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC23. Bus Invalidate Line Requests That Return Unexpected Data May Result in
L1 Cache Corruption
Problem:
When a Bus Invalidate Line (BIL) request receives unexpected data from a deferred reply, and a
store operation write combines to the same address, there is a small window where the L0 is
corrupt, and loads can retire with this corrupted data. This erratum occurs in the following
scenario:
•
A Read-For-Ownership (RFO) transaction is issued by the processor and hits a line in shared
state in the L1 cache.
•
The RFO is then issued on the system bus as a 0 length Read-Invalidate (a BIL), since it
doesn't need data, just ownership of the cache line.
•
This transaction is deferred by the chipset.
•
At some later point, the chipset sends a deferred reply for this transaction with an implicit
write-back response. For this erratum to occur, no snoop of this cache line can be issued
between the BIL and the deferred reply.
•
The processor issues a write-combining store to the same cache line while data is returning to
the processor. This store straddles an 8-byte boundary.
•
Due to an internal boundary condition, a time window exists where the L1 cache contains
corrupt data which could be accessed by a load.
Implication:
No known commercially available chipsets trigger the failure conditions.
Workaround:
The chipset could issue a BIL (snoop) to the deferred processor to eliminate the failure
conditions.
Status:
For the steppings affected, see the
Summary Tables of Changes.