Errata
R
38
Intel
®
Celeron
®
Processor in the 478-Pin Package Specification Update
AC50.
Memory Type of the Load Lock Different from Its Corresponding Store
Unlock
Problem:
A use-once protocol is employed to ensure that the processor in a multi-agent system may access
data that is loaded into its cache on a Read-for-Ownership operation at least once before it is
snooped out by another agent. This protocol is necessary to avoid a multi-agent livelock scenario
in which the processor cannot gain ownership of a line and modify it before that data is snooped
out by another agent. In the case of this erratum,
split load lock instructions incorrectly trigger the
use-once protocol. A load lock operation accesses data that splits across a page boundary with
both pages of WB memory type. The use-once protocol activates and the memory type for the
split halves get forced to UC. Since use-once does not apply to stores, the store unlock
instructions go out as WB memory type. The full sequence on the bus is: locked partial read (UC),
partial read (UC), partial write (WB), locked partial write (WB). The use-once protocol should
not be applied to load locks.
Implication:
When this erratum occurs, the memory type of the load lock will be different than the memory
type of the store unlock operation. This behavior (load locks and store unlocks having different
memory types) does not introduce any functional failures such as system hangs or memory
corruption.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
AC51.
A 16-bit Address Wrap Resulting from a Near Branch (Jump or Call) May
Cause an Incorrect Address to Be Reported to the #GP Exception Handler
Problem:
If a 16-bit application executes a branch instruction that causes an address wrap to a target
address outside of the code segment, the address of the branch instruction should be provided to
the general protection exception handler. It is possible that, as a result of this erratum, that the
general protection handler may be called with the address of the branch target.
Implication:
The 16-bit software environment which is affected by this erratum, will see that the address
reported by the exception handler points to the target of the branch, rather than the address of the
branch instruction.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
AC52.
ITP Cannot Continue Single Step Execution after the First Breakpoint
Problem:
ITP will not continue in single step execution after the first software breakpoint. ITP is unable to
reset the Resume Flag (RF) bit in the EFLAGS Register.
Implication:
The processor repeatedly breaks at the instruction breakpoint address instead of single stepping.
Workaround:
Execution after the break will continue, if you manually clear DR7 bit 1 (Global Breakpoint
Enable).
Status:
For the steppings affected, see the
Summary Tables of Changes
.
