Errata
R
Intel
®
Celeron
®
Processor in the 478-Pin Package Specification Update
27
AC19.
IA32_MC1_STATUS MSR ADDRESS VALID Bit May Be Set When No Valid
Address Is Available
Problem:
The processor should only log the address for L1 parity errors in the IA32_MC1_STATUS MSR
if a valid address is available. If a valid address is not available, the ADDRESS VALID bit in the
IA32_MC1_STATUS MSR should not be set. In instances where an L1 parity error occurs and
the address is not available because the linear to physical address translation is not complete or an
internal resource conflict has occurred, the ADDRESS VALID bit is incorrectly set.
Implication:
The ADDRESS VALID bit is set even though the address is not valid.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC20.
EMON Event Counting of x87 Loads May Not Work As Expected
Problem:
If a performance counter is set to count x87 loads and floating-point exceptions are unmasked, the
FPU Operand Data Pointer (FDP) may become corrupted.
Implication:
When this erratum occurs, the FPU Operand Data Pointer (FDP) may become corrupted.
Workaround:
This erratum will not occur with floating point exceptions masked. If floating-point exceptions
are unmasked, then performance counting of x87 loads should be disabled.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC21.
Software Controlled Clock Modulation Using a 12.5% or 25% Duty Cycle
May Cause the Processor to Hang
Problem:
Processor clock modulation may be controlled via a processor register
(IA32_THERM_CONTROL). The On-Demand Clock Modulation Duty Cycle is controlled by
bits 3:1. If these bits are set to a duty cycle of 12.5% or 25%, the processor may hang while
attempting to execute a floating-point instruction. In this failure, the last instruction pointer (LIP)
is pointing to a floating-point instruction whose instruction bytes are in UC space and which takes
an exception 16 (floating point error exception). The processor stalls trying to fetch the bytes of
the faulting floating-point instruction and those following it. This processor hang is caused by
interactions between thermal control circuit and floating-point event handler.
Implication:
The processor will go into a sleep state from which it fails to return.
Workaround:
Use a duty cycle other than 12.5% or 25%.
Status:
For the steppings affected, see the
Summary Tables of Changes.
