Intel Celeron Series, Спецификация

Страница: 22 / 50

Errata
R
22 Intel
®
Celeron
®
Processor in the 478-Pin Package Specification Update
AC9. Processor May Hang Due to Speculative Page Walks to Non-Existent
System Memory
Problem:
A load operation that misses the Data Translation Lookaside Buffer (DTLB) will result in a page-
walk. If the page-walk loads the Page Directory Entry (PDE) from cacheable memory and that
PDE load returns data that points to a valid Page Table Entry (PTE) in uncacheable memory the
processor will access the address referenced by the PTE. If the address referenced does not exist
the processor will hang with no response from system memory.
Implication:
Processor may hang due to speculative page walks to non-existent system memory.
Workaround:
Page directories and page tables in UC memory space which are marked valid must point to
physical addresses that will return a data response to the processor.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC10. Writing a Performance Counter May Result in Incorrect Value
Problem:
When a performance counter is written and the event counter for the event being monitored is
non-zero, the performance counter will be incremented by the value on that event counter.
Because the upper eight bits of the performance counter are not written at the same time as the
lower 32 bits, the increment due to the non-zero event counter may cause a carry to the upper bits
such that the performance counter contains a value about four billion (232) higher than what was
written.
Implication:
When this erratum occurs, the performance counter will contain a different value from that which
was written.
Workaround:
If the performance counter is set to select a null event and the counter configuration and control
register (CCCR) for that counter has its compare bit set to zero, before the performance counter is
written, this erratum will not occur. Since the lower 32 bits will always be correct, event counting
which does not exceed 232 events will not be affected.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC11. IA32_MC0_STATUS Register Overflow Bit Not Set Correctly
Problem:
The Overflow Error bit (bit 62) in the IA32_MC0_STATUS register indicates, when set, that a
machine check error occurred while the results of a previous error were still in the error reporting
bank (i.e. the valid bit was set when the new error occurred). In the case of this erratum, if an
uncorrectable error is logged in the error-reporting bank and another error occurs, the overflow bit
will not be set
Implication:
When this erratum occurs the overflow bit will not be set.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.