Intel Celeron Series, Спецификация

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Errata
R
32 Intel
®
Celeron
®
Processor in the 478-Pin Package Specification Update
AC33. CR2 May Be Incorrect or an Incorrect Page Fault Error Code May Be
Pushed onto Stack after Execution of an LSS Instruction
Problem:
Under certain timing conditions, the internal load of the selector portion of the LSS instruction
may complete with potentially incorrect speculative data before the load of the offset portion of
the address completes. The incorrect data is corrected before the completion of the LSS
instruction but the value of CR2 and the error code pushed on the stack are reflective of the
speculative state. Intel has not observed this erratum with commercially available software.
Implication:
When this erratum occurs, the contents of CR2 may be off by two, or an incorrect page fault error
code may be pushed onto the stack.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC34. ProSystem May Hang If a Fatal Cache Error Causes Bus Write Line (BWL)
Transaction to Occur to the Same Cache Line Address As an Outstanding
Bus Read Line (BRL) or Bus Read-Invalidate Line (BRIL)
Problem:
A processor internal cache fatal data ECC error may cause the processor to issue a BWL
transaction to the same cache line address as an outstanding BRL or BRIL. As it is not typical
behavior for a single processor to have a BWL and a BRL/BRIL concurrently outstanding to the
same address, this may represent an unexpected scenario to system logic within the chipset.
Implication:
The processor may not be able to fully execute the machine check handler in response to the fatal
cache error if system logic does not ensure forward progress on the system bus under this
scenario.
Workaround:
System logic should ensure completion of the outstanding transactions. Note that during recovery
from a fatal data ECC error, memory image coherency of the BWL with respect to BRL/BRIL
transactions is not important. Forward progress is the primary requirement.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC35. Processor Does Not Flag #GP on Non-Zero Write to Certain MSRs
Problem:
When a non-zero write occurs to the upper 32 bits of IA32_CR_SYSENTER_EIP or
IA32_CR_SYSENTER_ESP, the processor should indicate a general protection fault by flagging
#GP. Due to this erratum, the processor does not flag #GP.
Implication:
The processor unexpectedly does not flag #GP on a non-zero write to the upper 32 bits of
IA32_CR_SYSENTER_EIP or IA32_CR_SYSENTER_ESP. No known commercially available
operating system has been identified to be affected by this erratum.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.