Intel Celeron Series, Спецификация

Страница: 34 / 50

Errata
R
34 Intel
®
Celeron
®
Processor in the 478-Pin Package Specification Update
AC38. Glitches on Address or Data Strobe Signals May Cause System Shutdown
Problem:
When a Machine Check Exception is generated due to a glitch on the address or data strobe
signals, the exception may be reported repeatedly, resulting in system shutdown.
Implication:
If a glitch occurs on the address or data strobe signals, an operating system shutdown will occur if
Machine Check Exceptions (MCE) are enabled. IERR# assertion and shutdown will occur if
MCE is disabled.
Workaround:
Correct design and implementation of the processor system bus will remove the possibility of this
failure.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC39. CPUID Instruction Returns Incorrect Number of ITLB Entries
Problem:
When CPUID instruction is executed with EAX = 2 it should return a value of 51h in EAX[15:8]
to indicate that the Instruction Translation Lookaside Buffer (ITLB) has 128 entries. Due to this
erratum, the processor returns 50h (64 entries).
Implication:
Software may incorrectly report the number of ITLB entries. Operation of the processor is not
affected.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC40. A Write to an APIC Register Sometimes May Appear to Have Not Occurred
Problem:
With respect to the retirement of instructions, stores to the uncacheable memory-based APIC
register space are handled in a non-synchronized way. For example if an instruction that masks
the interrupt flag, e.g. CLI, is executed soon after an uncacheable write to the Task Priority
Register (TPR) that lowers the APIC priority, the interrupt masking operation may take effect
before the actual priority has been lowered. This may cause interrupts whose priority is lower
than the initial TPR, but higher than the final TPR, to not be serviced until the interrupt enabled
flag is finally set, i.e. by STI instruction. Interrupts will remain pending and are not
lost.
Implication:
In this example the processor may allow interrupts to be accepted but may delay their service.
Workaround:
This non-synchronization can be avoided by issuing an APIC register read after the APIC register
write. This will force the store to the APIC register before any subsequent instructions are
executed. No commercial operating system is known to be impacted by this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes