82571EB/82572EI EEPROM Information Guide
14
1.7.13
Initialization Control 3 (Word 14h/24h Upper Byte)
This word controls general initialization values.
Note:
If applicable, word 14h is used for LAN1 (Port 1/Port B). Word 24 is used for LAN0 (Port 0/Port
A).
Table 9. Initialization Control 3 (Word 14h/24h Upper Byte)
Bit
Name
Description
15
Reserved
Reserved. Set to 0b.
14
Multiple
Read Req
Ena
When set to 0b, the 82571EB/82572EI initiates one Tx DMA request
at a time. When set to 1b, the 82571EB/82572EI can initiate up to four
outstanding multiple TX DMA requests. This bit sets the default value
of the
MULR
field (bit 28) in the Transmit Control (TCTL) register.
13
LAN Flash
Disable
When set to 1b, disables the Flash logic. Flash access BAR in the PCI
configuration space is disabled.
12
Interrupt Pin
Controls the value advertised in the
Interrupt Pin
field of the PCI
configuration header for a given port. A value of 0b, reflected in the
Interrupt Pin
field, indicates that the 82571EB/82572EI uses INTA#; a
value of 1b indicates that the 82571EB/82572EI uses INTB#.
Note:
If a single port of the 82571EB/82572EI is enabled, this value is
ignored and the
Interrupt Pin
field of the enabled port reports INTA#
usage.
11
LAN Boot
Enable
A value of 1b disables the Expansion ROM BAR in the PCI
configuration space.
10
APM Enable
Initial value of
Advanced Power Management Wake Up Enable
in the
Wake Up Control register (WUC.APME). Mapped to CTRL[6] and to
WUC[0].
0b = Disable APM.
1b = Enable APM.
9:8
Link Mode
Initial value of the
Link Mode
field (bits 22 and 23) in the Extended
Device Control register (CTRL_EXT.LINK_MODE), specifying which
link interface and protocol is used by the MAC portion of the 82571EB/
82572EI.
00b - MAC operates in GMII/MII mode with internal copper PHY
(1000Base-T)
01b = Reserved.
10b = Reserved.
11b = MAC operates in TBI mode when using internal SerDes.
