January 2007
163
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Integrated Graphics Display Port
6.3.2
DVOB and DVOC Port Interface Routing Guidelines
For Intel 855GME chipset platforms, guidelines apply for both interfaces.
6.3.2.1
Length Mismatch Requirements
The routing guidelines presented in the following subsections define the recommended routing
topologies, trace width and spacing geometries, and absolute minimum and maximum routed
lengths for each signal group, which are recommended to achieve optimal SI and timing. In
addition to the absolute length limits provided in the individual guideline tables, more restrictive
length matching requirements are also provided that further restrict the minimum to maximum
length range of each signal group with respect to clock strobe, within the overall boundaries
defined in the guideline tables, as required to ensure adequate timing margins. These secondary
constraints are referred to as length matching constraints. The amount of minimum to maximum
length variance allowed for each group around the clock strobe reference length varies from signal
group to signal group depending on the amount of timing variation, which may be tolerated. Refer
to
for DVO length matching requirements.
Table 49. AGP/DVO Pin Muxing
DVO MODE
AGP MODE
DVO MODE
AGP MODE
DVO MODE
AGP MODE
DVOBD[0]
GAD[3]
DVOCD[0]
GAD[19]
MI2CCLK
GIRDY#
DVOBD[1]
GAD[2]
DVOCD[1]
GAD[20]
MI2CDATA
GDEVSEL#
DVOBD[2]
GAD[5]
DVOCD[2]
GAD[21]
MDVICLK
GTRDY#
DVOBD[3]
GAD[4]
DVOCD[3]
GAD[22]
MDVIDATA
GFRAME#
DVOBD[4]
GAD[7]
DVOCD[4]
GAD[23]
MDDCCDATA
GAD[15]
DVOBD[5]
GAD[6]
DVOCD[5]
GCBE#[3]
MDDCCLK
GSTOP#
DVOBD[6]
GAD[8]
DVOCD[6]
GAD[25]
DVOBCINT#
GAD[30]
DVOBD[7]
GCBE#[0]
DVOCD[7]
GAD[24]
DVOBCCLKINT
GAD[13]
DVOBD[8]
GAD[10]
DVOCD[8]
GAD[27]
ADDID[7]
GSBA[7]
DVOBD[9]
GAD[9]
DVOCD[9]
GAD[26]
ADDID[6]
GSBA[6]
DVOBD[10]
GAD[12]
DVOCD[10]
GAD[29]
ADDID[5]
GSBA[5]
DVOBD[11]
GAD[11]
DVOCD[11]
GAD[28]
ADDID[4]
GSBA[4]
DVOBCLK
GADSTB[0]
DVOCCLK
GADSTB[1]
ADDID[3]
GSBA[3]
DVOBCLK#
GADSTB#[0]
DVOCCLK#
GADSTB#[1]
ADDID[2]
GSBA[2]
DVOBHSYNC
GAD[0]
DVOCHSYNC
GAD[17]
ADDID[1]
GSBA[1]
DVOBVSYNC
GAD[1]
DVOCVSYNC
GAD[16]
ADDID[0]
GSBA[0]
DVOBBLANK#
GCBE#[1]
DVOCBLANK#
GAD[18]
DVODETECT
GPAR
DVOBFLDSTL
GAD[14]
DVOCFLDSTL
GAD[31]
DPMS
GPIPE#
Содержание 6300ESB ICH
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Страница 36: ...36 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide General Design Considerations...
Страница 102: ...102 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
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Страница 152: ...152 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines DDR SDRAM...
Страница 172: ...172 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Integrated Graphics Display Port...
Страница 190: ...190 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface...
Страница 246: ...246 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Intel 6300ESB Design Guidelines...
Страница 264: ...264 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Platform Clock Routing Guidelines...
Страница 298: ...298 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary...
Страница 318: ...318 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist...