Intel 6300ESB ICH, Руководство по конструкции

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Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
The two traces associated with each clock pair are length matched within the package, however
some additional compensation may be required on the motherboard in order to achieve the ±10-mil
length tolerance within the pair.
Between clock pairs the package length varies substantially. The motherboard length of each clock
pair must be length adjusted to tune out package variance. The total length including package shall
be matched to within ± 25 mils of each other. This may result in a clock length variance of as much
as 700 mils on the motherboard.
The clock lengths to DIMM1 may be up to 1.0 inch longer than the clock lengths to DIMM0.
The first step in determining the routing lengths for clocks and all other clock-relative signal
groups is to establish the target length for each DIMM clock group. These target lengths are shown
as X0 and X1 in
Figure 65 .These are the lengths to which all clocks within the corresponding
group are matched and the reference length values used to calculate the length ranges for the other
signal groups.
5.4.3.2 Clock Reference Lengths
The clock reference length for each DIMM clock group is calculated by first determining the
longest total clock length required to complete the clock routing. A table of clock package lengths
is provided in
Table 31 to assist with this calculation. After the longest total length is determined
for each clock group, this figure becomes a lower bound for the associated clock reference length.
At this point it is helpful to have completed a test route of the SDQ/SDQS bus such that final clock
reference lengths may be defined with consideration of the impact on SDQ/SDQS bus routability.
Some iteration may be required.
After the reference lengths X0 and X1 are defined then it remains to tune each clock pair’s
motherboard trace segment lengths as required such that the overall length of each clock equals the
associated clock reference length plus or minus the 25 mil tolerance. Again, the reference length
for the two sets of clocks shall be offset by the nominal routing length between DIMM connectors.