REMOTE OPERATION
5-30
Status byte
The Status Byte provides information about events and conditions within the instrument. It may be
read by a conventional Serial Poll or its value obtained as a response to the *STB? query. Bits 0 to
5 and bit 7 are each single-bit Summary Messages which may be of two types (or not used at all).
(i) Query
Status
−
a '1' indicates that an associated Queue is not empty and has data available to
be read.
(ii)
Status Register Summary
−
reports the occurrence of an enabled event monitored by a Status
Register Structure.
The Service Request Enable Register determines which of the bits can generate an SRQ; this
register may be set by *SRE or read by *SRE? If the bitwise-AND of the Status Byte and the
Enable Register is not zero the Flag Master Summary Status (<mss>) is True. Bit 6 of the Status
byte value read by *STB? holds <mss>. However bit 6 of the Status Byte when serial polled is the
Request For Service bit used to determine which device on the Bus has asserted SRQ, and is
cleared by a Serial Poll.
The IEEE 488.2 Standard defines bit 4 as Message Available (<mav>), the Queue Summary for the
Output Buffer, indicating whether any part of a Response Messages is available to be read. Bit 5 is
the Event Summary Bit (<esb>), the Summary Message from the Standard Event Status Register.
In 2026Q, bit 7 is a Queue Summary for the Error Queue. Bits 1, 2, and 3 are Status summaries for
the Instrument Status, Coupling Status and Hardware Status Registers. Bit 0 is unused.
The following is an explanation of how the Hardware Event Registers operate. Note that the
Coupling and Instrument Event Registers operate in a similar fashion, albeit the Instrument
Transition Filter uses negative-going transitions.
Each source (A and B) has its own Hardware Condition Register, Transition Filter, Hardware
Status Register and Hardware Status Enable Register.
For a particular source, the status of the hardware is continuously monitored by the Hardware
Condition Register. The Transition Filter determines which transition of the Hardware Condition
Register data bits will set the corresponding bit in the Hardware Status Register. In the case of the
Hardware Registers, a positive-going transition will set the bits.
The bits in the Hardware Status Register are latched. Once set they remain set, regardless of
subsequent changes in the associated condition bit until the Hardware Status Register is cleared by
being read (SOURCE B HSR?) or by the *CLS common command. Once cleared, a Hardware
Status Register bit will only be set again if a positive-going change in the Hardware Condition bit
occurs.
The Hardware Status Enable Register may be written to and read from. This register is
bitwise-ANDed with the Hardware Status Register and if the result is not zero the Summary
Message is true; otherwise the Summary Message is false. The Hardware Status Enable Register is
not affected by *CLS but is however clear at power-on.
The Summary Messages of each source are logically ORed, resulting in a combined Summary
Message. This combined Summary Message is reported in the Status Byte.
