ICS ICS-130, Руководство по эксплуатации

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DOC E10523 Rev.D

Interactive Circuits And Systems Ltd. 2000
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2. GENERAL DESCRIPTION
Figure 1 shows a simplified block diagram of the ICS-130 board. The board uses 32 16-bit
Sigma-Delta ADCs (Analog Devices AD7723) to provide simultaneous sampling at rates of
up to 1.2 Msamples/sec. on each channel. The oversampling ratio of the Sigma-Delta ADC
can be selected as 16 or 32.
To allow fast transfer of ADC data, the ICS-130 board includes a VME64 interface capable
of in excess of 70 MByte/s (i.e. D64 bus cycles), an optional P2 interface (VSB, RaceWay,
Skychannel, etc.), and a 32-bit front panel interface. The transfer rate of the FPDP interface
is fully programmable from 1 to 50 MHz. The VME64 interface circuitry uses the Tundra
Semiconductor (formerly Newbridge) SCV64 chip to support a Multiplexed Block Transfer
(MBLT) master/slave interface. The A32/D32, and A24/D32 protocols are also supported.
ADC data is buffered either in the 4 KSample FIFO (First-In First-Out memory) when data is
read-out via the FPDP or the P2 interface, or the dual-ported memories when data is read
out via the VMEbus. The sampling clock and the trigger can be either internal or external.
The internal ADC clock is user programmable in steps of less than 250Hz at the output
rate.
The ADCs can be operated either in continuous or capture modes. In the continuous mode,
data is continuously supplied to the selected interface upon application of a trigger signal
until the acquisition is disabled. In capture mode, a fixed number of samples are acquired
upon each application of the trigger. There are two ways in which this may be done. When
using pre-trigger storage, the ICS-130 stores samples continuously before the trigger and
acquires a programmable number of samples following the trigger (to a maximum of 32,768
samples/channel if all 32 channels are active). When pre-trigger storage is not used,
conversion starts at each application of the trigger and a programmable number of samples
(again, to a maximum of 32,768) are acquired.
In capture mode without pre-trigger storage, the acquisition count and buffer length may be
programmed separately. Thus it is possible to perform multiple capture sequences at each
occurrence of the trigger, until the buffer is filled to the programmed length.
The ICS-130 board can generate VMEbus interrupts at any user programmed interval
(number of samples acquired).
All power requirements of the ICS-130 are satisfied with standard VMEbus voltages.