ICS ICS-130, Руководство по эксплуатации

Страница: 24 / 61

DOC E10523 Rev.D

Interactive Circuits And Systems Ltd. 2000
20
TABLE 5.2 - SCV64 Register Descriptions
Register Offset Description
DMALAR:
DMA Local Address
0x0 This register contains the local bus address used by the SCV64 when performing
a VMEbus Master transfer. This register must be re-programmed to zero before
each Master transfer cycle is initiated.
DMAVAR:
DMA VMEbus Address
0x4 This register contains the VMEbus address accessed by the SCV64 when it is
performing a VMEbus Master transfer cycle. If not re-programmed between
cycles, it continues from the next consecutive address.
DMATC:
DMA Transfer Count
0x08 This register contains the DMA transfer count (Longwords) used by the SCV64
when it is performing a VMEbus Master transfer cycle. Register width is 20 bits
(DMATC<19:00>).
DCSR:
Control and Status
Register
0x0C The following describes the bits of the SCV64 Control and Status Register used
by the ICS-130. All other bits should be set to 0 during a write. The register
should always be cleared before starting to set up a DMA transfer.
DCSR<16> When asserted, this bit indicates an SCV64 configuration error
DCSR<12> A64 base address ready. Must be programmed to 1 after the
SA64BAR and MA64BAR registers have been programmed.
DCSR<5> If asserted, a bus error has occurred during a DMA transfer. Write a
'0' to clear the error.
DCSR<3:2> If either of these bits are asserted, the previous DMA cycle failed.
This can result from transferring too much data (See SCV Registers)
or BERR was asserted on the VMEbus during the transfer. Writing
'0' to these bits clears them.
DCSR<1> When asserted, the previous DMA cycle was successfully
completed. Writing '0' to this bit clears it.