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ICS ICS-130, Руководство по эксплуатации

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DOC E10523 Rev.D

 

 Interactive Circuits And Systems Ltd. 2000

 

26

7. Set DCSR<0>. This is the 'DMAGO' bit. The transfer will start at this point. 
8. At the completion of the transfer DMAGO will be read as clear. The DONE bit, 

DCSR<1>, should be read as set, and a VME interrupt will be asserted. The user 
should clear DCSR<1> in order to clear the interrupt. If a completion interrupt occurs 
but the DONE bit is not read as set, an error has occurred. The type of error is 
indicated by bits DCSR<3:2> and DCSR<5>. 

 
 
5.3.2 VMEbus DMA Slave 
 
When performing a VMEbus BLT or MBLT block transfer with the ICS-130 as the slave 
device, no set-up activity is necessary unless the programmer wishes to use A64 address 
cycles. The set-up procedure for doing this is given in section 5.3 above. 
 
The maximum possible block transfer is 256KB. When initiating a transfer, the programmer 
should ensure that there are sufficient samples available in the buffer, and that the buffer is 
of sufficient size for the size of transfer contemplated. 
 

5.4 ADC Data 
 
This section of the ICS-130's VMEbus memory map is used to read data from the ADC 
memory over the VMEbus. The VMEbus ADC Data area is 0x40000 bytes (256KB) in size. 
The ADC memory buffers are strictly read only. The same area of the memory map allows 
test pattern data to be written to the diagnostic FIFO, which is strictly write only. See section 
5.16 for details on using built in diagnostics. 
 
The data is organized as one sample in each 16-bit word, with "big endian" ordering. i.e. 
odd channels occupy the most significant 16 bits and even channels occupy the least 
significant 16 bits of a 32 bit longword. Channels are numbered from 1 to 32. 
 
The data area appears to the user as FIFO type memory. In other words, random access to 
samples in the memory is not available. Data access is always sequential regardless of the 
address used for read or write, as long as the address used falls within the ADC Data area. 
 
Each time a data word is read from the buffer, the data is removed from memory and buffer 
pointers are modified. The user must be careful to read the exact number of 32-bit words 
corresponding to the programmed buffer length, otherwise buffer overflow or underflow will 
occur. 
 
The user should perform a reset of the memory (ADC Reset register) after programming the 
ADC configuration and before enabling acquisition. This is necessary to ensure that the 
buffer pointers are correctly aligned prior to buffer access by the ADC circuits. 
 
Addresses presented by the bus master when reading data may be either incremental or 
repetitive (i.e. always the same address). Provided that addresses fall within the ADC Data 

Содержание ICS-130

Страница 1: ...cies or omissions Interactive Circuits and Systems Ltd reserves the right to make changes to products herein described to improve reliability function or design No patent rights are granted to any of...

Страница 2: ...DOC E10523 Rev D...

Страница 3: ...em Configuration 12 4 2 Jumper and Switch Settings 14 4 2 1 VMEbus Base Address Selection 14 4 2 2 P4 Local Bus Interface 16 5 PROGRAMMING MODEL 17 5 1 General Notes 17 5 2 SCV64 Registers 19 5 3 Perf...

Страница 4: ...gister 37 5 14 FPDP Clock Frequency Register 38 5 15 Arm Register 38 5 16 ADC Reset Register 38 5 17 Board Reset Register 39 5 18 Master Control Register MCR 39 5 18 1 MCR 09 00 Frame Length 39 5 18 2...

Страница 5: ...VxWorks and Solaris Use of one of these drivers is strongly recommended since they greatly simplify control and operation of the ICS 130 This will generally save the programmer much time since he she...

Страница 6: ...be either internal or external The internal ADC clock is user programmable in steps of less than 250Hz at the output rate The ADCs can be operated either in continuous or capture modes In the continuo...

Страница 7: ...SERIAL ADC 32 CHANNELS ADC ADC TO PARALLEL 1MSAMPLE 1MSAMPLE BUFFER BUFFER VME INTERFACE MULTI BOARD SYNCHRONIZATION EXTERNAL CLOCK EXTERNAL TRIGGER CONTROL 4KWORDS FIFO P2 MODULE FIFO FIFO FPDP INTER...

Страница 8: ...6x oversampling Minimum Channel Output Rate 31 25 kHz ch for 32 channels Maximum Decimation 256 Settling Time 1293 Fs 32x oversampling 541 Fs 16x oversampling Signal Noise Distortion Crosstalk 87dB Fs...

Страница 9: ...ut signal level is 2 Vpp differential i e 2 Vpp on each wire of the differential pair with an input impedance of 10k to ground on each input wire Figure 2 shows the input buffer stage for one channel...

Страница 10: ...igure 0 308Fo to 0 383Fo is shifted down to DC The choice of filter type and decimation oversampling ratio may be selected using the ADC Mode field of the ICS 130 Control register see section 5 7 11 F...

Страница 11: ...ion of the trigger Both external clock and trigger signals must conform to standard TTL levels and drive capability The relevant connections are listed in section 6 3 3 4 Data Path Selection The ICS 1...

Страница 12: ...pendantly set Data stored in the memory buffer will be divided into two sections data acquired before the application of the trigger and data acquired after the application of the trigger In the Conti...

Страница 13: ...dy condition 3 7 Cascading Multiple Boards The ICS 130 provides simultaneous sampling not only on all channels on one board but also on all channels across multiple boards The ICS 130 s PLL clock circ...

Страница 14: ...PDP cable Data from all selected channels are inserted into the FPDP Data frame in the correct time slot It is necessary to connect a cable between the P4 Local Bus connectors of each ICS 130 in order...

Страница 15: ...LED Function Colour Description 1 VME Access Green Illuminated at each valid VMEbus access to ICS130 2 P2 Access Green Illuminated at each valid P2 access to ICS 130 3 FPDP Out Green Illuminated at e...

Страница 16: ...ot where the ICS 130 is installed must be jumpered to ensure correct operation 4 1 System Configuration The ICS 130 is designed to allow simultaneous sampling across all channels on a board and also a...

Страница 17: ...DOC E10523 Rev D Interactive Circuits And Systems Ltd 2000 13 P2 P1 C O SW3 P7 P6 P4 P5 JP1 JP2 JP3 1 8 1 LED 1 LED 4 P3 K10385 2 Figure 3 ICS 130 Switch and Jumper Locations...

Страница 18: ...e End Slave end of the FPDP cable i e the ordering should be Master Mid slaves End Slave DSP If FPDP is not being used the position of the DSP board s in the chassis with respect to the ICS 130 boards...

Страница 19: ...of A31 to A27 allowing the base address to be set to any value between 0x08000000 and 0xF8000000 in increments of 0x8000000 The A32 base address is set as follows Switch VME A32 Address Bit JP1 6 A31...

Страница 20: ...tter s Other functions of the P4 Local Bus can be programmed by software using the Control Register see section 5 7 When connecting external clock and or trigger signals to a multiple board FPDP confi...

Страница 21: ...ponds to both SUPERVISORY and NON PRIVILEGED VMEbus cycles Individual bits in the 32 bit registers are referred to in braces e g ADCCR 0 corresponds to ADC Control Register bit 0 and ADCDEC 4 0 corres...

Страница 22: ...ADDRESS FRAME_LENGTH FRAME_COUNT ACQUISITION_COUNT BUFFER_LENGTH CHANNEL_COUNT IRQ ADC VME IRQ ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE ADC ADC TRIG SEL CLK SEL FPDP MASTER FPDP TERM ADC_MODE ACQ MOD...

Страница 23: ...the 64 bit base address are taken from the A32 base address values configured for the board as described in section 4 These jumper settings are loaded to the SCV64 VMEBAR register at power up but can...

Страница 24: ...nsfer cycle Register width is 20 bits DMATC 19 00 DCSR Control and Status Register 0x0C The following describes the bits of the SCV64 Control and Status Register used by the ICS 130 All other bits sho...

Страница 25: ...ve image 0 512K 1 1M 2 2M 3 4M VMEBAR 20 16 Base address of A24 slave image These bits form bits A23 A19 of base address Address bits A17 and A16 are forced to zero according to setting of VMEBAR 22 2...

Страница 26: ...ycles are used as determined by MODE 9 MODE 19 When set to 1 SCV64 Master transfer cycles are performed using MBLT D64 cycles on the VMEbus Must be cleared if MODE 9 is set to 1 or if MODE 18 is set t...

Страница 27: ...e VMEbus A64 master base address The remaining bits 31 0 are taken from the A32 image Before accessing this register MODE 12 must be set to 1 After accessing this register MODE 12 should be cleared VI...

Страница 28: ...24 VREQ 4 VMEbus Request Mode Control Condition 1 after reset 0 Fair 1 Demand VREQ 3 2 VMEbus Ownership Timer Time out Period Condition 3 after reset 0 Zero 1 2microsec 2 4microsec 3 8microsec VREQ 1...

Страница 29: ...Multiplexed Block transfer MBLT cycles may be used The order of programming for Master BLT and MBLT transfers is as follows All register references are to SCV64 registers For register details please...

Страница 30: ...read only The same area of the memory map allows test pattern data to be written to the diagnostic FIFO which is strictly write only See section 5 16 for details on using built in diagnostics The data...

Страница 31: ...nd the source of the interrupt If an interrupt is masked in the IMR the status of the associated event may still be read here 5 5 1 SR 0 VMEbus Master IRQ This bit reflects the interrupt status of the...

Страница 32: ...s not asserting IRQ 1 P2 Module is asserting IRQ 5 5 4 SR 3 IRQ This bit indicates that the ICS 130 is asserting a VMEbus interrupt from either source i e Master transfer completion or ADC Swing Buffe...

Страница 33: ...controller to generate VMEbus interrupts upon completion of a transfer IMR 0 VMEbus Master Interrupt Enable Mask READ WRITE 0 SCV64 Interrupts are disabled 1 SCV64 Interrupts are enabled 5 6 2 IMR 1...

Страница 34: ...sing an external trigger triggering occurs following the rising edge of the trigger signal The signal must remain high for at least one complete acquisition clock cycle CR 0 ADC Trigger Select READ WR...

Страница 35: ...can be read back from the swing buffer CR 2 Diagnostics enable READ WRITE 0 Diagnostic Mode disabled 1 Diagnostic Mode enabled 5 7 4 CR 3 P2 Enable This bit enables data output to the optional P2 Daug...

Страница 36: ...gnificant 16 bits of the data path CR 5 FPDP Word Width READ WRITE 0 Packed format two samples per Strobe cycle 1 Unpacked format one sample per Strobe cycle 5 7 7 CR 6 ADC Sampling Master Enable This...

Страница 37: ...selects between FPDP Master and FPDP Slave mode in a multiple board acquisition cluster when using FPDP output In the cluster or part cluster connected on a single FPDP cable only one board can be set...

Страница 38: ...Mode These bits select the operating mode of the Sigma Delta converters All converters on the board are programmed to the same mode CR 11 10 ADC Mode READ WRITE 0 0 32x oversampling Band Pass Filter...

Страница 39: ...he next rising edge of the external trigger input otherwise it starts with the first valid data after the trigger bit CR 13 has been set CR 14 Enable READ WRITE 0 ADC acquisition disabled 1 ADC acquis...

Страница 40: ...occur when the programmed length is reached The valid range of numbers that may be programmed to this register is 0 to 524287 The maximum value is equivalent to the maximum swing buffer capacity of 1M...

Страница 41: ...he new values to take effect 5 12 Frame Count Register Read Write Data for output to the FPDP and P2 interfaces is stored in two FIFO buffers which are arranged in a swing buffer mode of operation see...

Страница 42: ...Strobe frequency required is the sample output rate multiplied by the number of channels selected this value can be divided by two is packed output mode is used see section 5 7 6 The actual frequency...

Страница 43: ...a FPDP frame which is related to the total number of active channels across all boards This is value is given by the following expression W C x P 2 1 where C total number of channels selected on all I...

Страница 44: ...to the board in diagnostic mode the data flows through a hardware chain which includes a serial to parallel converter As a result the data read back has a different appearance from that written The d...

Страница 45: ...DOC E10523 Rev D Interactive Circuits And Systems Ltd 2000 41 APPENDICES...

Страница 46: ...the frame length MCR see section 5 18 4 6 Disable diagnostic mode see section 5 7 4 7 Clear Enable bit 4 8 Deassert internal trigger 5 Set interrupt mask register 6 Set decimation 7 Set acquisition co...

Страница 47: ...n identical operation is used with the FPDP Clock register to program the FPDP data rate Automatic calculation of the oscillator programming word is provided by the ics130calcFoxWord function and othe...

Страница 48: ...gister to be written by next data 0 Program Register Disabled 1 Program Register Enabled to Receive Data 0 1 Internal Output Disable 0 Output is VCO or fREF 1 Output is tri stated 0 2 Internal Multipl...

Страница 49: ...amming data Last Bit First Bit 1111 0101 0111 1110 111111 Transmit this serial bit stream Last Bit First Bit 10111 0101 00111 01110 01110111 The fields of the programming word are described in Table 6...

Страница 50: ...vco MHz 0000 50 80 1000 80 150 If the desired VCO frequency is exactly 80 MHz then either index value may be used since both limits are tested However the manufacturer recommends using the setting cor...

Страница 51: ...field before inserting a zero in the least significant bits of the Q value If the I field had contained a 1 in the most significant position the inserted zero would have been in a different position...

Страница 52: ...The example programming word for 12 8 MHz calculated in section 6 2 6 above is shown below Last Bit First Bit Programming word for 12 8 MHz 0x382370 0 0 1 1 1 0 0 0 0 0 1 0 0 0 1 1 0 1 1 1 0 0 0 0 3...

Страница 53: ...L 13 41 CHANNEL 13 26 CHANNEL 14 27 CHANNEL 14 11 CHANNEL 15 12 CHANNEL 15 42 CHANNEL 16 43 CHANNEL 16 Note 1 All other pins are connected to analog ground on the board 6 4 Analog 17 32 Connector Deta...

Страница 54: ...ANALOG INPUT 28 28 29 29 30 30 31 31 32 32 27 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 12 12 13 13 14 14 15 15 16 16 11 11 10 10 9 9 4 4 5 5 6 6 7 7 8 8 3 3 2 2 1 1 44 30 15 31...

Страница 55: ...l Ground 4 SYNC ADC Frame Sync In multiple board systems this signal is used by the sampling master to ensure the ADC s output syncronisation on all boards This signal is bussed from the sampling mast...

Страница 56: ...Signal used in FPDF board addressing 19 CHAN7 Signal used in FPDF board addressing 20 CHAN8 Signal used in FPDF board addressing 21 CHAN9 Signal used in FPDF board addressing 23 EXT_TRIG External Tri...

Страница 57: ...nt the need to fold the FPDP ribbon cable when connecting to the DSP board the cable is supplied with the connector at one end inverted The pinouts at the DSP FPDP connector are therefore reversed com...

Страница 58: ...5 1 2 6 3 7 4 8 73 77 79 75 74 78 80 76 3 1 A C D B PCB AREA BOARD CONNECTOR COMPONENT SIDE VIEW PIN 1 INDICATOR BOARD CONNECTOR BOARD EDGE VIEW 1 3 79 77 78 80 4 2 PIN 1 INDICATOR Cable numbers are...

Страница 59: ...17 PIO2 18 GND 19 PIO1 20 GND 21 RESERVED 22 GND 23 RESERVED 24 GND 25 PSTROBE 26 GND 27 PSTROBE 28 GND 29 SYNC 30 GND 31 DVALID 32 GND 33 D31 34 D30 35 GND 36 D29 37 D28 38 GND 39 D27 40 D26 41 GND...

Страница 60: ...6 2 FPDP Signals A description of FPDP signals is given in Table 6 4 Further details concerning the FPDP design are given in ICS INPUT Technical Note No 15 which is available from the factory or from...

Страница 61: ...as inputs or outputs PSTROBE PECL Data Strobe This signal along with PSTROBE are generated by the data source as an optional differential PECL Positive Emitter Coupled Logic data strobe PSTROBE is the...

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