ICS ELECTRONICS 4807, Инструкция по эксплуатации

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3.4 488.2 STATUS REPORTING STRUCTURE
The unit includes the expanded IEEE-488.2 Status Reporting Structure
shown in Figure 3-2. The expanded Status Reporting Structure conforms
to the SCPI 1994.0 Specification and builds on the IEEE 488.2 Standard
Status Reporting Structure with the addition of the Questionable and
Operation Registers. The Event and Status registers are controlled and
queried with the IEEE-488.2 common commands. The Status Byte
Register may also be read by serial polling the 4807/4867. The Questionable
and Operation registers are controlled and queried with SCPI commands.
As shown in Figure 3-2, IEEE 488.2 Service Request generation is a
multilevel function and is determined by the occurrence of an event that has
its corresponding enable bit set to '1'. Summary lines from the three event
registers cascade down to set bits in the Status Byte Register. When
enabled, the 4807/4867 pulls the SRQ line low to signal the bus controller
that an event has occurred and/or that the 4807/4867 needs service. The
2307/2367 sends its controller the SRM message to signal that it needs
service. The Event registers and the Output Queue are cleared when read
or by the
*CLS command.
3.4.1 Event Registers
An event register captures 0 to 1 transitions in its associated condition
register or in the standard event register. An event bit becomes TRUE (1)
when the associated condition bit makes logical 0 to 1 transition. Once an
event bit is set it is held until the event register is read or cleared with the
*CLS
command.
Each event register contains eight or sixteen bits. When the register is read,
its response is a decimal number that is the sum of the binary bit weights of
the bits that are logical 1s.
e.g., 23 decimal = 0001 0111 or 0000 0000 0001 0111 binary
Each event register bit has a corresponding enable bit. The enabling bits are
ANDed with the state of the event bits to create the summary condition in
the Status Byte Register. Unwanted conditions can be blocked from
generating Service Requests by setting their corresponding enabling bit to
a '0'. The enabling bits are set by writing the value equal to the sum of all
of the desired logic 1 bits to the enabling register. The value is normally