IBM x3850 X5, Руководство по внедрению

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24
IBM eX5 Implementation Guide
Figure 2-6 Relative memory performance based on DIMM placement (one processor and two memory cards shown)
2.3.3 Memory ranking
The underlying speed of the memory as measured in MHz is not sensitive to memory
population. (In Intel Xeon 5500 processor-based systems, such as the x3650 M2, if rules
regarding optimal memory population are not followed, the system BIOS clocks the memory
subsystem down to a slower speed. This situation is not the case with the x3850 X5.)
Unlike Intel 5500 processor-based systems, more ranks are
better
for performance in the
x3850 X5. Therefore, quad-rank memory is better than dual-rank memory, and dual-rank
memory is better than single-rank memory. Again, the frequency of the memory as measured
in MHz does not change depending on the number of ranks used. (Intel 5500-based systems,
such as the x3650 M2, are sensitive to the number of ranks installed. Quad-rank memory in
those systems always triggers a stepping down of memory speed as enforced by the BIOS,
which is not the case with the eX5 series.)
Performance test between ranks
With the Xeon 7500 and 6500 processors, having more ranks gives better performance. The
better performance is the result of the addressing scheme. The addressing scheme can
1
Each processor:
2 memory controllers
2 DIMMs per channel
8 DIMMs per MC
Mem Ctrl 1 Mem Ctrl 2
1.0
2
Mem Ctrl 1 Mem Ctrl 2
Each processor:
2 memory controllers
1 DIMM per channel
4 DIMMs per MC
0.94
Mem Ctrl 1
Memory card
DIMMs
Channel
Memory buffer
SMI link
Memory controller
3
Mem Ctrl 1 Mem Ctrl 2
Each processor:
2 memory controllers
2 DIMMs per channel
4 DIMMs per MC
0.61
Relative
performance
4
Mem Ctrl 1 Mem Ctrl 2
Each processor:
2 memory controllers
1 DIMM per channel
2 DIMMs per MC
0.58
5
Mem Ctrl 1 Mem Ctrl 2
Each processor:
1 memory controller
2 DIMMs per channel
8 DIMMs per MC
0.51
6
Mem Ctrl 1 Mem Ctrl 2
Each processor:
1 memory controller
1 DIMM per channel
4 DIMMs per MC
0.47
7
Mem Ctrl 1 Mem Ctrl 2
Each processor:
1 memory controller
2 DIMMs per channel
4 DIMMs per MC
0.31
8
Mem Ctrl 1 Mem Ctrl 2
Each processor:
1 memory controller
1 DIMM per channel
2 DIMMs per MC
0.29
1
0.94
0.61
0.51
0.47
0.31
0.29
0.58
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1 2 3 4 5 6 7 8
Configuration
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Memory configurations