IBM x3850 X5, Руководство по внедрению

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IBM eX5 Implementation Guide
The memory mezzanine is an optional component and orderable as listed in Table 4-6.
Table 4-6 x3690 X5 memory mezzanine option part number
Figure 4-13 shows the memory mezzanine and DIMMs.
Figure 4-13 Location of the memory DIMMs
With the Intel Xeon 6500 and 7500 processors, the memory controller is integrated into the
processor, as shown in the architecture block diagram in Figure 4-8 on page 126:
򐂰 Processor 0 connects directly to the memory buffers and memory DIMM sockets on the
system planar.
򐂰 Processor 1 connects directly to the memory buffers and memory in the memory
mezzanine.
If you plan to install the memory mezzanine, you are required to also install the second
processor.
The x3690 X5 uses the Intel scalable memory buffer to provide DDR3 SDRAM memory
functions. The memory buffers connect to the memory controller in each processor through
Intel Scalable Memory Interconnect links. Each memory buffer has two memory channels,
and the DIMM sockets are connected to the memory buffer with two DIMMs per memory
channel (2 DPC).
Option Feature code Description
60Y0323 9278 IBM x3690 X5 16-DIMM Internal Memory Expansion
Memory
mezz
a nine
Memory
mezzanine
Installing the
memory mezzanine
into the server
Memory DIMMs on the
system board