
HP E1563A and E1564A Register-Based Programming
137
Appendix B
Figure B-2. Slave Module Configuration.
TRIG:MODE
SLAVe0 pairs TTLT0 (sample) with TTLT1 (trigger)
A SLAVe0 module will function with other SLAVe0 modules and
the MASTer0 module.
1) The trigger source from the slave can be set
with the Trigger Source/Control Register bits
0,1,2,3,4,7,8,9,12,13,14, and 15.
.
2) SLAVe0 sets the TTLT0 line as if
the sample
source is TTLT0
and sets the TTLT1 line as if the
trigger source is
TTLT1
. These lines are simply
dedicated for synchronization between the
modules in the master-slave mode. You should
not use these lines for any other purpose.
MODE
Sample
signal
Trigger
signal
SLAVe0
TTLT0
TTLT1
SLAVe2
TTLT2
TTLT3
SLAVe4
TTLT4
TTLT5
SLAVe6
TTLT6
TTLT7
Содержание E1563A
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