
126
HP E1563A and E1564A Register-Based Programming
Appendix B
Trigger/Interrupt Level Channel 2 register and bit definition:
Trigger/Interrupt
Level Channel 3
Register
This register provides 8-bit data corrected for offset and gain in 2’s
compliment format.
Trigger/Interrupt Level Channel 3 register bits defined:
Trigger/Interrupt
Level Channel 4
Register
This register provides 8-bit data corrected for offset and gain in 2’s
compliment format.
Trigger/Interrupt Level Channel 4 register bits defined:
base + 2A
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Write*
MSB-
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
GL
Read**
MSB-
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
GL
*WRITE/**READ BITS (Trigger/Interrupt Level Channel 2 Register)
bit 0
GL
Greater than or Less than; “0” = >, “1” = <.
bits 15-8
D7-D0
data bits.
base + 2C
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Write*
MSB-
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
GL
Read**
MSB-
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
GL
*WRITE/**READ BITS (Trigger/Interrupt Level Channel 3 Register)
bit 0
GL
Greater than or Less than; “0” = >, “1” = <.
bits 15-8
D7-D0
data bits.
base + 2E
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Write*
MSB-
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
GL
Read**
MSB-
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
GL
*WRITE/**READ BITS (Trigger/Interrupt Level Channel 4 Register)
bit 0
GL
Greater than or Less than; “0” = >, “1” = <.
bits 15-8
D7-D0
data bits.
Содержание E1563A
Страница 8: ......
Страница 24: ...24 Digitizer Module Set up ...
Страница 84: ...84 Digitizer Command Reference ...
Страница 110: ...110 ...
Страница 138: ...138 HP E1563A and E1564A Register Based Programming Appendix B ...
Страница 156: ...156 HP E1563A and E1564A Verification Tests ...