HP 8340A, Руководство по обслуживанию

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8-122
Model 8340A - Service
fM
=
M Divider Output PRF (MHz)
N
=
N Divide Number
M
=
M Divide Number
f IF
=
M Divider Clock frequency (MHz)
20 MHz
=
N Divider Clock frequency
fN
=
fM when the loop is phase locke_d;
Therefore,
(4/N) (20 MHz)
=
(4/M) (fIF)
and fIF
=
[(M/N) 20] MHz for the phase locked
condition.
Because of the similarities of the M and N Dividers, only the N
Divider will be described in detail.
The N Divider circuit is clocked by a pulse train derived from the
input frequency (in this case the 20 MHz reference signal). The
divider outputs 4 pulses for each sequence of clock pulses which
add up to the N number. In other words, a pulse is output for each
N/4 or N/4 + 1 clock pulses. If dividing the N number by 4 leaves
no remainder, the number of clock pulses between output pulses is
determined solely by N/4. If there is a remainder, the number of
clock pulses between outputs is determined by N/4 and N/4 + 1
where N/4 +·1 replaces N/4 once for each unit in the remainder.
For example, if N
=
16, then N/4
=
16/4
=
4 with a remainder R
=
O. An output pulse occurs for each 4 clock pulses. If N
=
19, then
N/4
=
19/4
=
4 with R
=
3. An output pulse occurs once with a
spacing of 4 clock pulses and three times with a spacing of
5
clock pulses.
a. Counting Operation and Control. Refer to the schematic block
diagram and the following figure and table entitled Divider
Operation, and consider the example of N
=
16. At the beginning of
a divide sequence (clock 1), the 4 most significant bits (MSB) of
Scans by HB9HCA and HB9FSX