HP 8340A, Руководство по обслуживанию

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INTRODUCTION
Model 8340A - Service
A39 PHASE LOCK LOOP 3 (PLL3) UPCONVERTER,
CIRCUIT DESCRIPTION
The function of the A39 Phase Lock Loop 3 Upconverter is to mix
160 MHz with the output of the A40 PLL 2 VCO (.1 5 to 6 MHz) and
output the sum of the two frequencies. This is done using a
phase-lock loop which has a closed loop bandwidth of
approximately 10 kHz.
FREQUENCY MULTIPLIER (X 1.6) A
In order to offset the PLL2 output by 160 MHz, a 160 MHz
reference signal must be generated. The frequency multiplier x
1.6 generates 160 MHz by dividing the 100 MHz input reference
signal by five and then selecting the eighth harmonic.
U3 is an ECL bi-qinary counter that is connected so that the
output skips one pulse every five input counts as can be seen
from the waveforms in Figure 8C-19.
threshold
100 MHz REF
Figure
BC-19. A39 PLL3
Frequency Multiplier Waveforms
U3 OUTPUT
The net effect of the pulse skipping is to produce a double
narrow pulse (refer to Q3 output in figure· 8C-19) at a 20 MHz
rate. This gives better results than simply dividing the 100 MHz
reference by 5 to obtain a 20 MHz pulse train because the
narrower pulses generate stronger harmonics than a 20 MHz pulse
train would.
8-217
Scans by HB9HCA and HB9FSX