Model 8340A - Service
and Cll will delay the HIGH-to-LOW transition at Ul5B pin 10 by
several nanoseconds to allow the clock to reach Ul5B before the
HIGH on pin 10 input goes away. This leaves Ul5B set, as desired.
If there is a rate multiplier output, as in State
#
3, then RlO
and Cll are not nearly as important. In this case there are two
things that are forcing TP7 LOW through U3A; the rate
multiplier(s) Ul/U2 and HSWALLOW. Since the rising edge of the
signal at TP7 will clock Ul5B, then the last signal to be removed
from forcing TP7 LOW will be the signal that clocks Ul5B. As
shown in Figure 8C-14, STATE
#
3, the rising edge of the signal
at TP7 occurs after HSWALLOW has gone LOW. The reason is that
both the signals that are forcing TP7 LOW are beginning to be
removed at the same input clock pulse. HSWALLOW will be removed
much sooner than the rate multiplier Ul/U2 since it is an ECL
device, so Ul/U2 are actually clocking Ul5B. Since Ul and U2 have
very long TTL delays compared to ECL, the effect of the RlO and
Cll time delay on HSWALLOW is insignificant. The Ul5B pin 10
input will still go low before the clock pulse from Ul/U2
arrives.
PHASE/FREQUENCY DETECTOR
E
The Phase/Frequency Detector compares the divider output with a 5
MHz reference frequency. When the two inputs are in phase, the
outputs are ECL HIGH, approximately +4 volts, with very narrow
pulses at a 5 MHz rate. When the inputs are the same frequency
but different in phase, one output line is a pulse with a width
corresponding to the phase difference; the other output is HIGH
with very narrow pulses. For a difference in input frequencies,
the outputs are pulses of varying widths, but average de voltage
levels will be different. The sign of this de voltage is set by
which frequency is higher.
REFERENCE DIVIDE BY
2
F
U7C is an input buffer amplifier which generates the proper level
for ECL (approximately +3 volts LOW and +4 volts HIGH). R5,R6,
and C4 ,provide de feedback around U7C to enable it to oper�te as
a linear amplifier. Ul5A divides the 10 MHz input by 2 and
applies this 5 MHz to the phase/frequency detector.
8-201
Scans by HB9HCA and HB9FSX
Содержание 8340A
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