HP 8340A, Руководство по обслуживанию

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Model 8340A - Service
approximately± SV, one of the two comparators will turn on its
associated clock. The clock will either increment or decrement the
counter which will increase or decrease the current out of the DAC.
The DAC output will further correct the tuning voltage for the
discriminator, thereby reducing the voltage on the integrator
capacitot to within the
+sv window. To hold the discriminator
tuning voltage during the sweep, the FET is turned off.
VCO RANGE AND STEP-SIZE
The PLL2 VCO is a varactor-tuned transistor oscillator with a
tuning range of 75-150 MHz. The phase-lock loop allows it to be
programmed in 5 kHz steps between 100-150 MHz. The sweep width
can be as wide as 25 MHz (PLL2 VCO sweeps down in frequency) and
as narrow as 500 kHz. The output of the VCO is divided by several
digital frequency dividers to be sent to various destinations.
These divided outputs are shown in Table 8C-2:
OUTPUT
Table 8C-2. 20-30 Loop Frequency Range vs. Divider Configuration
OF PLL2 VCO FREQ RANGE DESTINATION
Direct output
of
vco 75-150 MHz PLL2 FRACTIONAL DIVIDER
Divided by
5
15-30 MHz
used
as a 20-30 output
Divided
by 25 3-6 MHz
Sent to
PLL3
Upconverter
Divided by 500 150-300 kHz
Sent to PLL3
Upconverter
DIVIDER
There are two digital frequency dividers used in the A42 PLL2
DIVIDER. One is a fixed divide-by-20 that is used to create a 500
kHz signal from a 10 MHz reference (the 10 MHz reference is from
the A29 Reference Phase Detector). This 500 kHz signal is the
reference signal for the PLL2 loop and is used as one input to
the phase-detector.
The second divider is a fractional divider that uses
pulse-swallowing techniques to divide the PLL2
vco
output by
numbers between 200.01 and 300.00.
Refer to the "Frequency Range an1 CW Mode Accuracy" Performance
Test for use as a troubleshooting aid.
8-1 71/8-1 72
Scans by HB9HCA and HB9FSX