Rev. 1.00
78
August 29, 2018
Rev. 1.00
79
August 29, 2018
HT45F6530
AC Voltage Regulator Flash MCU
HT45F6530
AC Voltage Regulator Flash MCU
than the maximum A/D clock period which may result in inaccurate A/D conversion values. Refer to
the following table for examples, where values marked with an asterisk * show where special care
must be taken, as the values may be exceeding the specified A/D Clock Period range.
f
SYS
A/D Clock Period (t
ADCK
)
SACKS[2:0]
=000
(f
SYS
)
SACKS[2:0]
=001
(f
SYS
/2)
SACKS[2:0]
=010
(f
SYS
/4)
SACKS[2:0]
=011
(f
SYS
/8)
SACKS[2:0]
=100
(f
SYS
/16)
SACKS[2:0]
=101
(f
SYS
/32)
SACKS[2:0]
=110
(f
SYS
/64)
SACKS[2:0]
=111
(f
SYS
/128)
1MHz
1μs
2μs
4μs
8μs
16μs *
32μs *
64μs *
128μs *
2MHz
500ns
1μs
2μs
4μs
8μs
16μs *
32μs *
64μs *
4MHz
250ns *
500ns
1μs
2μs
4μs
8μs
16μs *
32μs *
8MHz
125ns *
250ns *
500ns
1μs
2μs
4μs
8μs
16μs *
A/D Clock Period Examples
Controlling the power on/off function of the A/D converter circuitry is implemented using the
ADCEN bit in the SADC0 register. This bit must be set high to power on the A/D converter. When
the ADCEN bit is set high to power on the A/D converter internal circuitry a certain delay, as
indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if
no pins are selected for use as A/D inputs, if the ADCEN bit is high, then some power will still be
consumed. In power conscious applications it is therefore recommended that the ADCEN is set low
to reduce power consumption when the A/D converter function is not being used.
Conversion Rate and Timing Diagram
A complete A/D conversion contains two parts, data sampling and data conversion. The data
sampling which is defined as t
ADS
takes 4 A/D clock cycles and the data conversion takes 12 A/D
clock cycles. Therefore a total of 16 A/D clock cycles for an external input A/D conversion which is
defined as t
ADC
are necessary.
Maximum single A/D conversion rate=A/D clock period/16
The accompanying diagram shows graphically the various stages involved in an external channel
input signal analog to digital conversion process and its associated timing. After an A/D conversion
process has been initiated by the application program, the microcontroller internal hardware will
begin to carry out the conversion, during which time the program can continue with other functions.
The time taken for the A/D conversion is 16 t
ADCK
clock cycles where t
ADCK
is equal to the A/D clock
period.
ADCEN
START
ADBZ
SACS[3:0]
(SAINS[3:0]=0000)
off
on
off
on
t
ON2ST
t
ADS
A/D sampling time
t
ADS
A/D sampling time
Start of A/D conversion
Start of A/D conversion
Start of A/D conversion
End of A/D
conversion
End of A/D
conversion
t
ADC
A/D conversion time
t
ADC
A/D conversion time
t
ADC
A/D conversion time
0011B
0010B
0000B
0001B
A/D channel
switch
A/D Conversion Timing – External Channel Input
