Rev. 1.00
76
August 29, 2018
Rev. 1.00
77
August 29, 2018
HT45F6530
AC Voltage Regulator Flash MCU
HT45F6530
AC Voltage Regulator Flash MCU
A/D input as when the pin-shared function control bits enable an A/D input, the status of the port
control register will be overridden.
If the SAINS3~SAINS0 bits are set to “0000”, “0100”, or “1100~1111”, the external analog channel
input is selected to be converted and the SACS3~SACS0 bits can determine which actual external
channel is selected to be converted. If the SAINS3~SAINS0 bits are set to “0001~0011”, the V
DD
voltage with a specific ratio of 1, 1/2 or 1/4 is selected to be converted. If the SAINS3~SAINS0 bits
are set to “0101~0111”, the PGA output voltage with a specific ratio of 1, 1/2 or 1/4 is selected to be
converted. If the SAINS3~SAINS0 bits are set to “1000~1001”, the OCP operational amplifier 0 or
1 output voltage is selected to be converted. Note that when the internal analog signal is selected to
be converted, then the external channel signal input will automatically be switched off regardless of
the SACS field value. It will prevent the external channel input from being connected together with
the internal analog signal.
SAINS[3:0] SACS[3:0]
Input Signals
Description
0000, 0100,
1100~1111
0000~0101
AN0~AN5
External pin analog input
0110~1111
—
Floating, no external channel is selected
0001
xxxx
V
DD
Internal A/D converter power supply voltage
0010
xxxx
V
DD
/2
Internal A/D converter power supply voltage/2
0011
xxxx
V
DD
/4
Internal A/D converter power supply voltage/4
0101
xxxx
V
R
Internal A/D converter PGA output voltage
0110
xxxx
V
R
/2
Internal A/D converter PGA output voltage/2
0111
xxxx
V
R
/4
Internal A/D converter PGA output voltage/4
1000
xxxx
V
OPA0O
Internal OCP Operational Amplifier 0 output voltage
1001
xxxx
V
OPA1O
Internal OCP Operational Amplifier 1 output voltage
1010~1011
xxxx
GND
Reserved, connected to ground.
"x": Don't care.
A/D Converter Input Signal Selection
A/D Converter Operation
The START bit in the SADC0 register is used to start the AD conversion. When the microcontroller sets
this bit from low to high and then low again, an analog to digital conversion cycle will be initiated.
The ADBZ bit in the SADC0 register is used to indicate whether the analog to digital conversion
process is in progress or not. This bit will be automatically set to 1 by the microcontroller after an
A/D conversion is successfully initiated. When the A/D conversion is complete, the ADBZ will be
cleared to 0. In addition, the corresponding A/D interrupt request flag will be set in the interrupt
control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be
generated. This A/D internal interrupt signal will direct the program flow to the associated A/D
internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller
can poll the ADBZ bit in the SADC0 register to check whether it has been cleared as an alternative
method of detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock f
SYS
, can be
chosen to be either f
SYS
or a subdivided version of f
SYS
. The division ratio value is determined by
the SACKS2~SACKS0 bits in the SADC1 register. Although the A/D clock source is determined
by the system clock f
SYS
and by bits SACKS2~SACKS0, there are some limitations on the A/D
clock source speed range that can be selected. As the recommended range of permissible A/D clock
period, t
ADCK
, is from 0.5μs to 10μs, care must be taken for system clock frequencies. For example,
as the system clock operates at a frequency of 8MHz, the SACKS2~SACKS0 bits should not be set
to 000, 001 or 111. Doing so will give A/D clock periods that are less than the minimum or larger
