199
Bit 1—Timer Output Level Setting B (TOB): Sets the value output from the FTIOB pin after
reset until the first compare match B (TCNT and GRB matching signal) is generated. After a
compare match is generated, FTIOB outputs the value specified in timer I/O control register 0
(IOB2 to IOB0).
Bit 1: TOB
Description
0
FTIOB is 0
(Initial value)
1
FTIOB is 1
Bit 0—Timer Output Level Setting A (TOA): Sets the value output from the FTIOA pin after
reset until the first compare match A (TCNT and GRA matching signal) is generated. After a
compare match is generated, FTIOA outputs the value specified in timer I/O control register 0
(IOA2 to IOA0).
Bit 0: TOA
Description
0
FTIOA is 0
(Initial value)
1
FTIOA is 1
12.2.3
Timer Interrupt Enable Register W (TIERW)
Bit
7
6
5
4
3
2
1
0
OVIE
—
—
—
IMIED
IMIEC
IMIEB
IMIEA
Initial value
0
1
1
1
0
0
0
0
Read/Write
R/W
—
—
—
R/W
R/W
R/W
R/W
TIERW is an 8-bit read/write register that enables or disables the TCNT overflow interrupt request
and general register (GRA, GRB, GRC, and GRD) compare match or input capture interrupt
requests.
TIERW is initialized to H'70 by a reset.
Bit 7—Timer Overflow Interrupt Enable (OVIE): Enables or disables the FOVI interrupt
requested by the OVF flag of TSRW when OVF is set to 1.
Bit 7: OVIE
Description
0
FOVI interrupt requested by OVF flag is disabled
(Initial value)
1
FOVI interrupt requested by OVF flag is enabled
Содержание H8/3660
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Страница 408: ...392 18 5 Output Load Circuit VCC 2 4 kΩ 12 kΩ 30 pF LSI output pin Figure 18 7 Output Load Condition ...
Страница 457: ...441 DEC VIN CH3 to CH0 A D converter Internal data bus Figure C 17 Port B Block Diagram PB7 to PB0 ...