Revision F • 3/12
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5 Service
front panel displays, and for the delay processing.
It’s programmed by the data stored in a 2 MB
Flash Memory chip (U16). The board’s firmware
code can be updated, as required, by plugging a
USB thumb drive with updated data files into the
USB port (J6) on the rear panel.
The update procedure is detailed
in a Code Update section, later in
this chapter.
A 128 MB SDRAM chip (U26) is used for the
Diversity Delay and for the optional Profanity
Delay. About 47 seconds of total delay time is
available.
A GPS antenna signal (input on J20) feeds a
Copernicus GPS receiver (U1). The center conduc-
tor of the type-F connector carries a current
l5 volts to power the GPS antenna. The
GPS receiver has 1 PPS (pulse
per second) clock and GPS lock
outputs. If the GPS receiver is not
locked onto the GPS satellites, the
FPGA then generates a GPS Un-
lock alarm.
Two VCXOs (made up of Y2, Y3, and U25) gen-
erate a 20 MHz and a 22.5792 MHz clock which
are phase locked to the GPS 1 PPS signal. The 20
MHz clock is divided in half to generate the 10
MHz clock output, which is further divided by
3,125 to generate a 3,200 Hz clock, which is com-
pared with the 1 PPS signal in a phase detector
circuit. Another 3,200 Hz clock is generated by
dividing down the 22.5792 MHz clock. This clock
is phase locked to the 3,200 Hz clock generated
by the 20 MHz VCXO.
The 10 MHz clock
output (on J11) is used
to synchronize an HD
Radio Exciter, when
it’s co-located with the
HDE-200, along with
the 1 PPS clock out-
put, which is sent through a tri-state octal buffer
(U10) to J9. These signals are typically only used
when the HD Radio Exciter is co-located with the
HDE-200.
The 22.5792 MHz clock is divided by two to
generate a 11.2896 MHz master clock for the
FPGA, the delay memory, and the AES transmit-
ters. This clock is called the 256fs clock since it is
256 times the 44.1 kHz AES audio sample rate,
which is called the fs clock. The 11.2896 MHz
clock is also divided by 4 to
create a 64fs clock, which is used
by the AES receiver chips. It is
divided by 256 to generate the
44.1 kHz master clock which is
sent through a line driver (U10)
to rear panel jack, J10.
An Ethernet switch chip (U24) connects the
Linux CPU (plugged into SODIMM socket J8) to
the HD Radio DSP board (via the internal CAT-5
cable) and to the three rear panel RJ45 jacks (Port
1, Port 2, Port 3). These ports can be used to di-
rectly connect to an HD Radio Importer, admin
computer, STL, HD Radio Exciter, or to a facility
network switch.
The iButton socket (J35) connects to the FPGA.
An iButton is a 1-wire® device programmed with
a specific code to unlock
optional features on the
HDE-200. The iButton
uses +3.3 volts and must
be installed for the op-
tional features to func-
tion.
