
Revision F • 3/12
H
A
R
R
I
S
C
O
R
P
O
R
A T
I
O
N
5-3
5 Service
5.1.3 UPGRADE KIT PARTS
Profanity Delay (HARHDE200-PROFAN)
Harris # Description or Use
Qty.
21-801-1
iButton for Profanity Delay
1
71-1441
Installation documentation
1
Arbitron PPM Interface (HARHDE200-PPM)
Harris # Description or Use
Qty.
21-801-2
iButton for Arbitron PPM
1
71-1441
Installation documentation
1
90-2200
Interface Cable Assy
1
Arbitron PPM & Profanity Delay
(HARHDE200-PROF/PPM)
Harris # Description or Use
Qty.
21-801-3
iButton (PPM & Profanity Delay) 1
71-1441
Installation documentation
1
90-2200
Interface Cable Assy
1
5.2 Technical Overview
The HDE-200 consists of four PCAs:
· Interface Controller
· Linux CPU
· Front Panel Display
· HD Radio DSP
The HDE-200 block diagram is shown below.
The part identifiers in this section are silkscreened
onto the circuit boards.
The power supply—a com5 VDC “line
lump” type held captive within the chassis, plugs
into J23 on the Interface Controller. The 5 volt
output is filtered, regulated and/or current lim-
ited by U14, U15, U17, U32, U38, U39, U40, and
U41 to derive the four supply voltages (+1.2, +1.8,
+3.3 and +5 volts) used in the HDE-200.
5.2.1 Interface Controller
A Field Programmable Gate Array (FPGA),
U33, controls signal routing, remote I-O logic, the
BNC
BNC
TRS
RJ-45
RJ-45
RJ-45
RJ-45
44-pin D-Sub
RJ-45
A
12-pin
MOD IV
PHASE
PHASE
20.00MHZ
22.58MHZ
LOOPS
BNC
1PPS
3-PIN
PHASE LOCKED
SPI 0 Status/Command
SSC Audio
DELAY MEMORY
MAIN DELAY
LEFT
RIGHT
~IRQ0
~IRQ1
~SPI0_GA_PROG
SERIAL-PORT A
SERIAL-PORT
B
~SPI0_FPGA_CNFG
44.1KHZ
Processor Reset
~RST_9260
iButton
socket
10.00MHZ
1PPS
HEAD
PHONE
AMP
FILTER
INTERNAL
POWER
~RST_9260
BYPASS RELAYS
DC
POWER
99-1820
HD Radio
DSP PCA
90-1446
Ribbon Cable
901 012 1293
Front Panel
Display Assembly
50-31
+5VDC
Supply
90-2131-2
CAT-5 Cable
Broadcom Multi-Port
Ethernet Switch
Linux CPU
(plugs into
SODIMM socket)
Xilinx Spartan 3 FPGA
Copernicus
GPS Receiver
F
USB Host
9260
Processor
with SRAM
and DRAM
Ethernet
I/O
Main
Delay
In
USB
10 MHz
1 PPS
44.1 kHz
H/P Monitor
GPS
Main
Delay
Out
MPS
Audio
In
Ref
Mon
Out
Post Delay
Loop I/O
Remote I/O
Logic
Port
1
Port
2
Port
3
XLR-F
XLR-M
XLR-M
XLR-F
~RST_9260
AC Input
(110-240 VAC
50/60Hz)
Power
HDE-200 Block Diagram
B