GE Advantium CT9800, Технические публикации

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GE MEDICAL SYSTEMS CT 9800 QUICK SYSTEM
Rev. 3
Direction 18000
8-6-10
11) INITIALIZE GATE ARRAYS WITH SCAN SET STRING SPIN
Description:
SCAN SET is a function of all gate arrays (except IOP) that allows all internal flip-flops and registers to
be tied together in a 1 bit serial string that forms a long shift register. In this section of deadstarts, the
serial registers are “SPUN” or loaded with data, for each board that has SCAN SET capability.
The purpose of SCAN SET in the Deadstarts is twofold. First, each gate array (with the exception of IOP
chips) must have mode bits initialized before the AP starts executing the APM operating system. Mode
bits are flip-flops that are configured in each chip to “ENABLE” the specific function of the chip
depending on it’s location in the AP. Each gate array can perform many different circuit functions. Data
registers are also initialized along with the mode bits. Secondly, SCAN SET effectively tests each gate
array for basic functionality. This does not include any ALU or operating functions of the arrays, but
does include testing every flip-flop on each array for proper operation. The output of the string for each
board is compared against the input to ensure all arrays on the card are basically alive. A failure will
report the circuit card that failed.
Error conditions:
The scan setable cards are MMC, SMP, ACP, ACU, CMU (CACHE UPPER), CML (CACHE
LOWER), BPB0 (BACKPROJECTOR 0), BPB1 (BACKPROJECTOR 1), and the IOC. SCAN SET is
very primitive electrically. The only signals required to SCAN SET an array are the 25mhz clock, test
enable, phase enable, clock stop, serial in, and serial out. In 90% of the failures occurring during
Scan Set, there is a problem getting one of these signals to one of the arrays on the card - broken
rework wires or cold solder joints. The other 10% is due to gate array failure, with the most likely
cause being
Electro-Static-Discharge “ESD”.
The CMOS arrays used in the AP are the most
static sensitive components in the 9800 QUICK system.
a) FAILURE OF ALL BOARDS
The IOC card contains the SSC gate array that controls all scan set activity. In addition, it is the
source of clocks and all other signals required to scan set. A failure of all boards would indicate
an IOC problem.
b) FAILURE OF TWO OR MORE BOARDS
Clocks from the IOC are daisy-chained through a set of two, three, or four cards. A failure on a
set of cards could indicate an IOC driver problem, backpanel, or the first card that gets the clock
from the identified set. Card clock sets are: (in order)
1) IOC, SMP, ACP (the IOC does feed a clock back to itself)
2) ACU, CACHE-U, CACHE-L, MMC
3) BP0, BP1
In every case the components under suspicion are the IOC, backpanel, and the first card in
the failed set. Although more unlikely (two independent failures rarely happen at the same
time), it could be that each identified card has a failure.
c) FAILURE OF A SINGLE CARD
The failure of a single card is the most common. Probable failed components are the circuit card
identified by the failing test, IOC, and Backplane - in that order.